Performance of FPGA implementation of bit-split architecture for intrusion detection systems

Jung, Hong-Jip; Baker, Zachary K.; Prasanna, Viktor K.

doi:10.1109/ipdps.2006.1639434

Cited by 12 publications

(1 citation statement)

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“…A new technique has been introduced to have a memory efficient architecture. In this the state machine is converted into state transition tables which lead to parallel search with packets [11]. Still state machine based techniques (Finite Automata and Non-Finite Automata) are growing at a fast rate to have more and more efficient search with optimal parameters A function that takes up any function of random length and produces a digital data of fixed length, then it is termed as the hash function.…”

Section: Literature Reviewmentioning

confidence: 99%

High Speed and Low Power Architecture for Network Intrusion Detection System

Brindha¹,

Athappan²

2016

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The tremendous growth in the field of modern communication and network systems places demands on the security. As the network complexity grows, the need for the automated detection and timely alert is required to detect the abnormal activities in the network. To diagnose the system against the malicious signatures, a high speed Network Intrusion Detection System is required against the attacks. In the network security applications, Bloom Filters are the key building block. The packets from the high speed link can be easily processed by Bloom Filter using stateof-art hardware based systems. As Bloom Filter and its variant Counting Bloom Filter suffer from False Positive Rate, Multi Hash Counting Bloom Filter architecture is proposed. The proposed work, constitute parallel signature detection improves the False Positive Rate, but the throughput and hardware complexity suffer. To resolve this, a Multi-Level Ranking Scheme is introduced which deduces the 13%-16% of the power and increases the throughput to 23%-30%. This work is best suited for signature detection in high speed network.

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Section: Literature Reviewmentioning

confidence: 99%

High Speed and Low Power Architecture for Network Intrusion Detection System

Brindha¹,

Athappan²

2016

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A Memory-Efficient and Modular Approach for String Matching on FPGAs

Prasanna

2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-In Network Intrusion Detection Systems (NIDSs), string matching demands exceptionally high performance to match the content of network traffic against a predefined database of malicious patterns. Much work has been done in this field; however, they result in low memory efficiency 1 . Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-ofthe-art designs cannot support large dictionaries without using high-latency external DRAM. We propose a novel Memory efficient Architecture for large-scale String Matching (MASM), based on pipelined binary search tree. With memory efficiency close to 1 byte/char, MASM can support a dictionary 2 of over 4 MBytes, using a single FPGA device. The architecture can also be easily partitioned, so as to use external SRAM to handle even larger dictionaries of over 8 MBytes. Our implementation results show a sustained throughput of 3.5 Gbps, even when external SRAM is used. The MASM module can be simply duplicated to accept multiple characters per cycle, leading to scalable throughput with respect to the number of characters processed in each cycle. Dictionary update involves only rewriting the memory content, which can be done quickly without reconfiguring the chip.

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