Performance of demountable solder joints for no-insulation superconducting coils produced by vacuum pressure impregnation

Abstract

No-insulation HTS stack coils show both increased thermal and electrical stability, and present a simplified geometry for the integration of demountable joints. Demountability is a desirable feature for many superconducting applications including fusion magnets, which motivate this research. In this work, a novel vacuum pressure impregnation (VPI) solder process was developed to couple superconducting paths via a low resistance, mechanically simply, demountable joint for a non-insulated coil design. The three low temperature solders considered were $\mathrm{In_{52}Sn_{48}}$ (mp = 118$^{\circ}$C), $\mathrm{In_{100}}$ (mp = 156.6$^{\circ}$C), and $\mathrm{Ga_{100}}$ (mp = 29.8$^{\circ}$C), all with a lower melting point than the $\mathrm{Pb_{37}Sn_{63}}$ (mp = 183$^{\circ}$C) used to solder the HTS tapes into the coil, thus allowing for the advantages of solder in the joint, yet facilitating demountability without disturbing the primary solder in the non-insulated coil stack. A multidisciplinary campaign was undertaken to design, build, test and identify the major challenges with these small-scale demountable solder joints. A multi probe voltage tap system was used to infer the effective resistances to exit a superconducting stack, cross the solder layer, and enter the second superconducting stack, at 77 K. The experimental resistivities show good agreement with a newly developed finite element model that breaks down domains to the level of individual layers of an HTS tape. When taking into account the thermal degradation that can occur to the HTS stacks during the VPI processes, the normalized joint resistances are found to be 528, 668, 671 $n\Omega \cdot cm^2$ for $\mathrm{In_{100}}$, $\mathrm{In_{52}Sn_{48}}$ and $\mathrm{Ga_{100}}$ solders, respectively. The benchmarked finite element model is used to predict normalized joint resistances for fusion-relevant temperatures and magnetic fields using a 100 $\mu m$ solder layer thickness, finding 40, 124, 100 $n\Omega \cdot cm^2$ for the respective solders; these results are competitive with the lowest resistance cable joints presented in the literature.

Performance degradation due to thermal cycling in soldered Faraday and SuperPower HTS tape stacks

“…Particularly in the latter case, these linear components can be separated by small non-linear regions. Therefore, by using only the linear component directly preceding the superconducting transition, the fitting is simplified and this improves the parameter prediction accuracy for I c and n. Note that it is shown in our previous work [6] that the low current I-V linear slope is associated with the purely ohmic resistance, where as higher slopes include contributions from the superconducting transition region of various tapes; this is due to non-uniform filling of the tape stack based upon current taking the lowest resistance paths. Thus in the cases with multiple slopes prior to the superconducting transition, the linear component directly preceding the transition and therefore associated with the joint at the transition point, is truly considered an effective resistance.…”

“…At each red dot, there is a single voltage tap approximately above the central HTS tape in the stack. At currents close to the collective stack superconducting transition, it is assumed there is high uniformity of current in each tape such that the transverse voltage differences between tapes are negligible [6]. This implies that the point at the transverse midplane of the tape stack is a good representation of the overall average stack voltage, enabling measurements of voltage differences along the stack length.…”