Performance investigation of hetero material (InAs/Si)‐based charge plasma TFET

Abstract

The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential candidate to replace the conventional TFET as it offers fabrication simplicity and its proficiency to be used for ultra-low-power applications. A charge plasma TFET (CPTFET) with hetero materials for enhancement of device performance is presented. For this, a narrow bandgap material (InAs) is used instead of silicon in source region for reducing the lateral tunnelling distance at the source/channel interface. The reduced tunnelling width at the source/ channel junction enables higher band-to-band tunnelling generation rate, thus the device offers higher ON-state current. In this context, a comparative study of CPTFET and hetero junction charge plasma TFET (H-CPTFET) has been performed in terms of transfer characteristic (I ds-V gs), transconductance (g m), gate-to-drain capacitance (C gd), cutoff frequency (f T) and gain-bandwidth product. In addition to this, the effect of variation in channel length (L g) and drain to source voltage (V ds) on the DC and analogue/radio frequency performance of H-CPTFET is also analysed.

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

“…2 b and 3 b , respectively. In this state, a wide barrier is present between the valence band at the source region and the conduction band at the channel region resulting in impediment of BTBT [18]. In this context, the aforementioned barrier has been reduced to some extent for HJ ADG DLTFET by employing a lower bandgap material in the source region, but still, the charge carrier has not been able to tunnel across the source–channel interface.…”

“…To intensify the on current of DL TFET, miscellaneous techniques have been reported in the literature such that hetero‐dielectric gate [15], work‐function engineered drain [16], insertion of the metal layer in the spacer length between gate and source electrodes [17], material engineering involving the usage of different materials for source and channel regions [18]. Furthermore, to suppress ambipolarity numerous approaches have been stated such as low‐drain doping in the drain region [19], hetero‐dielectric BOX structure [20], underlap and overlap of gate–drain [21, 22], and metal layer insertion in the spacer between the gate and source metal electrodes [23], creation of an oversized back gate in the double‐gate DL TFET [24].…”

Role of grooving angle of 14‐nm‐InAs channel quantum well MOSFETs in improving analogue/RF and linearity performance

“…Among the III-V semiconductors, InAs has been extensively investigated as the channel material for MOSFETs because it exhibits outstanding electron mobility of 33,000 cm 2 /Vs at room temperature, which is, for instance, 20 times higher than that of Si. Additionally, the bandgap of InAs is much lower compared to that of Si, allowing supply voltage scaling and the injection velocity of electrons in InAs is larger than that of those in Si, thereby rendering InAs transistors attractive, particularly at advanced technology nodes [7][8][9][10][11][12][13][14][15][16][17][18]. However, due to the lower effective mass of electrons, InAs has lower density-of-states which limits the drain current [19].…”

Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

“…Recently, some novel structures of TFETs such as the dual material control gate chargeplasma-based tunnel FET (DMCG-CPTFET) [8] , and drain work function engineered doping-less charge plasma TFET [9] are presented for the suppression of ambipolarity. To combat the issue of low current driving capability, a number of different technologies have been reported in the literature with gate work function engineering [10] , high-k gate dielectrics engineering [11] , lower bandgap materials employed in source engineering such as germanium (Ge) source [12] and indium arsenide (InAs) source TFETs [13,14] , and some novel structures of TFETs such as gate-all-around triple metal (GAA TM) TFETs [15] , p-n-p-n TFETs [16] , a hetero-junction at the source-channel TFETs [17,18] , a hetero-stacked TFET [19] , electrically doped TFET (ED-TFET) based on polarity control [20] , and so on. Recently, ferroelectric (FE) insulator engineering of TFET has been used due to the fact that the ferroelectric gate dielectric produces a negative capacitance (NC) effect, which leads to the enhanced electric field at the source-channel junction [21][22][23][24] .…”