Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter

Li, Yunlu; Wang, Dazhi; Han, Wei; Tan, Sen; Guo, Xiao

doi:10.1109/access.2016.2614008

Cited by 41 publications

(28 citation statements)

References 33 publications

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“…The complex vector filter is actually a double-input dual-output complex transfer function. The complex vector filter is shown in Figure 1, where H(s) is the transfer function of the complex vector filter with the following expression [26] H(s) = R(s) + jQ(s)…”

Section: Complex Vector Filter Overviewmentioning

confidence: 99%

“…According to the modeling method in reference [26], the real part R(s) of dqDMTOGI(s) is employed instead of dqDMTOGI for mathematical modeling. Its modeling accuracy will be verified later by simulation reference [26], the real part R(s) of dqDMTOGI(s) is employed instead of dqDMTOGI for mathematical modeling. Its modeling accuracy will be verified later by simulation Figure 13.…”

Section: Small-signal Modelmentioning

confidence: 99%

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An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions

Hui

Wang

2018

Energies

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Synchronous-reference-frame phase-locked loop (SRF-PLL) is widely used in grid synchronization applications. However, under unbalanced, distorted and DC offset mixed grid conditions, its performance tends to worsen. In order to improve the filtering capability of SRF-PLL, a modified three-order generalized integrator (MTOGI) with DC offset rejection capability based on conventional three order generalized integrator (TOGI) and an enhanced delayed signal cancellation (EDSC) are proposed, then dual modified TOGI (DMTOGI) filtering stage is designed and incorporated into the SRF-PLL control loop with EDSC to form a new hybrid filter-based PLL. The proposed PLL can reject the fundamental frequency negative sequence (FFNS) component, DC offset component, and the rest of harmonic components in SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to the EDSC reducing the number of DSC operators. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameter design guidelines are given. Experimental results are included to validate the effectiveness and robustness of the proposed PLL.

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Section: Complex Vector Filter Overviewmentioning

confidence: 99%

Section: Small-signal Modelmentioning

confidence: 99%

An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions

Hui

Wang

2018

Energies

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“…Furthermore, grid frequency does not always stay at its nominal value. To maintain the phase tracking accuracy under distorted grid voltages conditions, various filtering technique were used to remove disturbances at the cost of slowing down the transient response, which may violate the requirement on settling time in common grid codes [19][20][21][22][23]. The block diagram of SRF-PLL is depicted in Figure 3.…”

Section: Introductionmentioning

confidence: 99%

“…However, LPF-based PLL can only attenuate but not eliminate the disturbance component. To achieve good disturbance rejection, the bandwidth of LPF-based PLL must be significantly reduced, which results in a large settling time [23]. Compared with LPF, MAF can totally remove a specific set of disturbances, which depends on its window length (T ω ).…”

Section: Introductionmentioning

confidence: 99%

A Modified DSC-Based Grid Synchronization Method for a High Renewable Penetrated Power System Under Distorted Voltage Conditions

Yang

et al. 2019

Energies

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With the increasing penetration of renewable energy, a weak grid with declining inertia and distorted voltage conditions becomes a significant problem for wind and solar energy integration. Grid frequency is prone to deviate from its nominal value. Grid voltages become more easily polluted by unbalanced and harmonic components. Grid synchronization technique, as a significant method used in wind and solar energy grid-connected converters, can easily become ineffective. As probably the most widespread grid synchronization technique, phase-locked loop (PLL) is required to detect the grid frequency and phase rapidly and precisely even under such undesired conditions. While the amount of filtering techniques can remove disturbances, they also deteriorate the dynamic performance of PLL, which may not meet the standard requirements of grid codes. The objective of this paper is to propose an effective PLL to tackle this challenge. The proposed PLL is based on quasi-type-1 PLL (QT1-PLL), which provides a good filtering capability by using a moving average filter (MAF). To accelerate the transient behavior when disturbance occurs, a modified delay signal cancellation (DSC) operator is proposed and incorporated into the filtering stage of QT1-PLL. By using modified DSCs and MAFs in a cascaded way, the settling time of the proposed method is reduced to around one cycle of grid fundamental frequency without degrading any disturbance rejection capability. To verify the performance, several test cases, which usually happen in high renewable penetrated power systems, are carried out to demonstrate the effectiveness of the proposed PLL. China [7,8], and caused many wind turbines to be tripped off. This highly impacted the operation of power distribution and renewable energy utilization. The grid frequency is prone to deviate from its nominal value since the inertia of the grid decreases. Grid voltages contain an amount of undesired components, such as fundamental frequency negative sequences (FFNSs) and harmonic components, which results in unbalanced and distorted grid conditions. It is an essential requirement for a renewable energy power converter to maintain stable operation with high performance under such conditions. To achieve this goal, a proper grid synchronization method is needed for all grid-connected applications. It is a big challenge for a grid synchronization method to extract grid frequency and phase information under such adverse conditions.

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“…Frequency and phase angle of the injected current and voltage have to be accommodated simultaneously to achieve unity power factor . In network‐connected applications, phase‐locked loops (PLLs) are the most widely used synchronization techniques . The reason for this can be the extra benefits of synchronous reference frame phase‐locked loop (SRF‐PLL) such as simplicity of implementation, resistant performance, and its reliability.…”

Section: Introductionmentioning

confidence: 99%

Investigating the stability of phase-locked loop in network-connected applications affected by microgrid-side and network-side parameters

Ahmadzadeh

Mortazavi

Saniei

2018

Int Trans Electr Energ Syst

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In most today's power systems, microgrids are connected to the network through a grid-interface converter. In these converters, the phase-locked loop (PLL) is the most popular technique for network synchronization. This paper investigates the dynamic performance and the stability of synchronous reference frame PLL influenced by various factors. These factors include the network-side and microgrid-side parameters. Similar to the effect of networkside factors, the effect of microgrid components also plays an important role in the stability of the PLL. Given that the stability of PLL affected by microgrid-side parameters have not been studied yet, so in this article, after a detailed analytical modeling of microgrid components (including the production power fluctuations, energy storage system, microgrid-side loads, and controller parameters), the stability of PLL affected by different microgrid-side parameters has been evaluated. In addition, with the aim of achieving a criterion for the assessment of PLL stability, also, based on the proposed criterion, the rate of exchanged output power is determined for the grid-interface converter with the aim of guaranteeing the stability of PLL. KEYWORDS analytical modeling, grid-interface converter, microgrid, network-side and microgrid-side parameters, phase-locked loop stability, proposed PLL stability criteria List of symbols and abbreviations: R L1 , The equivalent resistance of power losses related to the switches of supercapacitor converter; R L2 , The equivalent resistance of power losses related to the switches of battery converter; φ net , The phase created by the existence of the network and load impedances in network frequency; φ P , The phase created by the existence of the network and load impedances in output Frequency of PLL; C eq , The equivalent capacitance of DC bus; C sc , The equivalent capacity of supercapacitor; R p , The equivalent parallel resistance of supercapacitor; R s , The equivalent series resistance of supercapacitors; u sc , The supercapacitor voltage; u b , The battery voltage; i sc , The supercapacitor current; i b , The battery current; L 22 , The inductance of output filter of supercapacitor converter; L 11 , The inductance of output filter of battery converter; d 2 , The duty cycle of supercapacitor converter; d 1 , The duty cycle of battery converter; Z LL , The local load impedance; Z net , The network impedance; u net , The network voltage; i Gl , Differences between the current of consumable load and the current produced by distributed generation sources; τ 1 , The time constant of low-pass filter; τ 2 , The time constant of band-pass filter; I * l1d , d-component reference current of grid-interface converter; i l1d , dcomponent instantaneous current of grid-interface converter; I * l1q , The component reference current of grid-interface converter; i l1q , The component instantaneous current of grid-interface converter; d d , The d-component duty cycle of grid-interface converter; d q , The q-component duty cycle of grid-interface co...

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Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter

Cited by 41 publications

References 33 publications

An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions

An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions

A Modified DSC-Based Grid Synchronization Method for a High Renewable Penetrated Power System Under Distorted Voltage Conditions

Investigating the stability of phase-locked loop in network-connected applications affected by microgrid-side and network-side parameters

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