Performance implications of single thread migration on a chip multi-core

Constantinou, Theofanis; Sazeides, Yiannakis; Michaud, Pierre; Fetis, Damien; Seznec, André

doi:10.1145/1105734.1105745

Cited by 71 publications

(47 citation statements)

References 23 publications

(27 reference statements)

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“…However, there are important differences between their work and ours as will be explained later. Constantinou et al [9] analyzed the implications of migrating threads among cores and concluded that not invalidating the branch predictor reduces the penalty of resuming execution with cold structures. Li et al [22], [23] studied the design space of multicore systems.…”

Section: Background and Related Workmentioning

confidence: 99%

Understanding the Thermal Implications of Multi-Core Architectures

Chaparro

González²,

Magklis

et al. 2007

IEEE Trans. Parallel Distrib. Syst.

108

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Abstract-Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level parallelism (TLP). In addition, it is a power and complexity-effective way of taking advantage of the huge number of transistors that can be integrated on a chip. On the other hand, today's higher than ever power densities have made temperature one of the main limitations of microprocessor evolution. Thermal management in multicore architectures is a fairly new area. Some works have addressed dynamic thermal management in bi/quad-core architectures. This work provides insight and explores different alternatives for thermal management in multicore architectures with 16 cores. Schemes employing both energy reduction and activity migration are explored and improvements for thread migration schemes are proposed.

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Section: Background and Related Workmentioning

confidence: 99%

Understanding the Thermal Implications of Multi-Core Architectures

Chaparro

González²,

Magklis

et al. 2007

IEEE Trans. Parallel Distrib. Syst.

108

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“…For example, consider the scenario in Figure 2, where Thread 2, Thread 3 and Thread 4 all participate in migration, and form a cyclic dependency chain. Such migrations can be complex to implement in practice -in fact, global thread migration is impractical for many reasons: (i) increased performance overheads because of the amount of network traffic required to perform the migration, and because a larger number of cores start with cold caches [3]; (ii) increased Example illustrating both global thread migration (high overhead and implementation complexity) and complexity-effective thread swapping.…”

Section: B Greedy Thread Swappingmentioning

confidence: 99%

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms

Ravishankar

Ananthanarayanan

Garg

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-Thread migration (TM) is a recently proposed dynamic power management technique for heterogeneous multi-processor system-on-chip (MPSoC) platforms that eliminates the area and power overheads incurred by fine-grained dynamic voltage and frequency scaling (DVFS) based power management. In this paper, we take the first step towards formally analyzing and experimentally evaluating the use of power-aware TM for parallel data streaming applications on MPSoC platforms. From an analysis perspective, we characterize the optimal mapping of threads to cores and prove the convergence properties of a complexity effective greedy thread swapping based TM algorithm to the globally optimal solution. The proposed techniques are evaluated on a 9-core FPGA based MPSoC prototype equipped with fully-functional TM and DVFS support, and running a parallelized video encoding benchmark based on the Motion Picture Experts Group (MPEG-2) standard. Our experimental results validate the proposed theoretical analysis, and show that the proposed TM algorithm provides within 8% of the DVFS performance under the same power budget, and assuming no overheads for DVFS. Assuming voltage regulator inefficiency of 80%, the proposed TM algorithm has 9% higher performance than DVFS, again under the same total power budget.

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“…Constantinou et al considered performance effects of migrating a process among cores on a multicore processor [3]. They studied performance effects of warming up L1 instruction and data caches on the new core before migrating the process to that core (as opposed to leaving the caches cold).…”

Section: Related Workmentioning

confidence: 99%

Performance Implications of Cache Affinity on Multicore Processors

Kazempour

Fedorova

Alagheband

2008

Lecture Notes in Computer Science

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Abstract. Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity is exploited by OS schedulers: they tend to reschedule processes to run on a recently used processor. On conventional (unicore) multiprocessor systems, exploitation of cache affinity improves performance. It is not yet known, however, whether similar performance improvements would be observed on multicore processors. Understanding these effects is crucial for design of efficient multicore scheduling algorithms. Our study analyzes performance effects of cache affinity exploitation on multicore processors. We find that performance improvements on multicore uniprocessors are not significant. At the same time, performance improvements on multicore multiprocessors are rather pronounced.

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Performance implications of single thread migration on a chip multi-core

Abstract: High performance multi-core processors are becoming an industry reality. Although multi-cores are suited for multithreaded and multi-programmed

Cited by 71 publications

References 23 publications

Understanding the Thermal Implications of Multi-Core Architectures

Understanding the Thermal Implications of Multi-Core Architectures

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms

Performance Implications of Cache Affinity on Multicore Processors

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