Performance Impact of Task Mapping on the Cell BE Multicore Processor

Abstract

Abstract. Current multicores present themselves as symmetric to programmers with a bus as communication medium, but are known to be non-symmetric because their interconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermore, we ran exhaustive mapping experiments, and we observed that (1) performance variations can be significant between consecutive runs, and (2) performance forecasts based on intuitive interconnect behavior models are far from accurate even for a simple communication pattern.

A Server Model for Reliable Communication on Cell/B.E.

“…provides superior performance. Authors in [18] attempt to map a simple task with communication to SPEs of Cell/B.E., and the test results show that the performance bottleneck might be caused by the interconnection between memory and cores. [19] ports the RODAS solver to Cell/B.E.…”