Performance evaluations of stacked CSP memory modules

2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium

2009

In the past decade, compact components such as Chip Scale Packages and flip chips were the work horses of miniaturization. However, emerging applications are now demanding even higher packaging density. In order to fulfill this requirement, three dimensional packaging was evolved. Advantages of three dimensional packaging structure include minimal conductor length and reduce speed limiting inter chip interconnects. In the past, this packaging approach was relegated to memory devices with relatively low power (flash). Recent focus, however, has been to extend the applications of stacked packages to include high performance memory, DRAM, logic-memory stack, system in a package etc. Stacked packages can be package-on-package or die stacked (with several dice inside the same casing) or both. It is common in a mobile phone that the stacked CSP is mounted on a circuit board and there is no space for air circulation. Depending on the power, due to the torturous heat flow path, it can result in high temperatures of the packaged die and the thermal specifications of the package can be easily exceeded. Hence there is a need for thermal simulation of a variety of packaging architecture for applications of interest. The objective of this paper was to perform thermal characterization of a commercially viable PoP. In order to model this PoP, flip chip logic die package was considered as the bottom package and two memory dice stacked package was considered as the top package. Eleven different scenarios were taken into consideration for the numerical analysis. Permutations of 0.1, 0.2, 0.3 and 1, 2 and 3 W memory die and logic die was considered respectively Additional two cases are also described. Steady state analysis was performed based on which guidelines were provided. For the analysis commercially available FEA tool was considered.

Section: Introductionmentioning

confidence: 99%

Thermal design optimization of a package on package

Menon

Karajgikar

2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium

2009

“…Figure A.3 shows the Pro-E model of the PoP. Once the assembly is created it is imported to Ansys [82]. Owing to the symmetric nature of the problem, an octant model is considered.…”

Section: Package Description and Modeling Proceduresmentioning

confidence: 99%

Effect of Structural Design Parameters on Wafer Level CSP Ball Shear Strength and Their Influence on Accelerated Thermal Cycling Reliability

Lakhkar

Viswanadham

Volume 5: Electronics and Photonics

2009

Ball shear testing is typically conducted in Wafer level chip scale package (WLCSP) fabrication to estimate the strength of the solder ball attachment. Generally, the solder ball shear strength is dependent on the solder ball size, pad size, solder/pad interface treatment, reflow temperature and time. Solder ball strength is also a function of ram speed and height at which the ball is sheared with respect to the wafer. Recent investigations suggest that ball shear test is being used as an indicator for board level reliability of assemblies. In current market lead time for launching a new product is very short. Unfortunately, it takes several weeks to qualify a new product by board level qualification process. If there is a methodology through which one can predict the board level performance by extrapolating the wafer level test, it will save great amount of resources in testing and millions of dollars worth of testing time. In the first part of this study, we conducted a wafer level ball shear test. A DOE was created for varying wafer level structural parameters like solder ball size and type. Ball shear tests and Accelerated thermal cycling have similar failure signatures of compression on inner side and tension on outer side. Thus, for specific cases there is a possibility of correlating the two failure methodologies based on their failure signatures. Strain rate for ball shear test was determined based on shear speed and solder pad diameter. Strain rate for accelerated thermal cycling was determined based on difference in CTE between board and package. In this paper, results from ball shear test and accelerated thermal cycling are compared to find correlations for specific cases. The correlations derived from this study are statistical and empirical.

Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor

Dewan-Sandur

Kaisare

56th Electronic Components and Technology Conference 2006

et al.

The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging Integrated Circuit (IC) packaging requirements.Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only. In this paper, the focus is on stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (Package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. Geometries needed were generated by using Pro/Engineer ® Wildfire ™ 2.0 as a Computer-Aided-Design (CAD) tool and were transferred to ANSYS ® Workbench ™ 10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100ºC, which is an unacceptable value due to wafer level electromigration. A discussion is presented in what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results were evaluated in the light of market segment requirements.