[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications
DOI: 10.1109/cmpeur.1991.257469
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Performance evaluation of processor architectures for robotics

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Cited by 9 publications
(3 citation statements)
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“…Now, we want to update our interface to use it in a PCI bus [3,4] based computer thus increasing the communication bandwidth between the PC and the MC68000 system. Furthermore, as the i486 processor, Pentium II [5] and latter processors are also suitable to emulate the MC68000 bus and substitute this processor in industrial applications [6].…”
Section: Introductionmentioning
confidence: 99%
“…Now, we want to update our interface to use it in a PCI bus [3,4] based computer thus increasing the communication bandwidth between the PC and the MC68000 system. Furthermore, as the i486 processor, Pentium II [5] and latter processors are also suitable to emulate the MC68000 bus and substitute this processor in industrial applications [6].…”
Section: Introductionmentioning
confidence: 99%
“…The reason is that the DSPs execute pure filter algorithms very efficiently, but inte- grating action and the necessary wind-up protection contains logic that breaks the floating point pipeline in a very undesirable way. The M68040 CPU, on the other hand, is better suited for general control tasks [13]. Sampling frequencies up to 1 kHz were used on the master CPU, whereas frequencies up to 24 kHz was used on the DSP part.…”
Section: Motor Control Examplementioning
confidence: 99%
“…The compiler therefore inserts sufficiently many nop-instructions before a functions call (and before the return of a function) in order to empty the pipeline. Clearly, the computing performance then decreases to that of an ordinary microprocessor [5]. This was the motivation for our C++/assembly interface, mentioned in Section 2 and utilized below.…”
Section: Pipelining In a Floating Point Dspmentioning
confidence: 96%