Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function

Ranka, Deepesh; Rana, Ashwani K.; Yadav, Rakesh Kumar; Yadav, Kamalesh; Giri, Devendra

doi:10.5121/vlsic.2011.2102

Cited by 11 publications

(2 citation statements)

References 12 publications

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“…Hole current density is more pronounced in source side rather than drain side. It is due the hole collection or accumulation in source side [16]. These holes are injected from drain electrode.…”

Section: Figmentioning

confidence: 99%

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

Deivakani¹,

M.G

Anitha

et al. 2021

Preprint

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Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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Section: Figmentioning

confidence: 99%

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

Deivakani¹,

M.G

Anitha

et al. 2021

Preprint

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“…As the MOSFET gate length reaches the nanometer regime, short channel effects (SCEs) become more and more significant, thus, new circuit design technologies and various device concepts are becoming extensively attractive (Alam and Abdullah, 2012;Bahari et al, 2011;Kurniawa et al, 2010;Loussier et al, 2009;Tienda et al, 2008). Multiple-gate structures and silicon on insulator (SOI) are promising structures to overcome SCEs in nanometre-scaled MOSFETs (Gaffar et al, 2011;Ranaka et al, 2011). Conventional CMOS technology is facing greater challenges in terms of scaling due to *Corresponding author.…”

Section: Introductionmentioning

confidence: 99%

Quantum simulation study of gate-all-around (GAA) silicon nanowire transistor and double gate metal oxide semiconductor field effect transistor (DG MOSFET)

Hosseini

Fathipour²,

Faez³

2012

Int. J. Phys. Sci.

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In this paper, electrical characteristics of the double gate metal oxide semiconductor field effect transistor (DG MOSFET) and that of gate all around silicon nanowire transistor (GAA SNWT) have been investigated. We have evaluated the variations of the threshold voltage, the subthreshold slope, draininduced barrier lowering, ON and OFF state currents when channel length decreases. Quantum mechanical transport approach based on non-equilibrium Green's function method (NEGF) has been performed in the frame work of effective mass theory with taking into account exchange-correlation effects. Its simulation consists of solutions of the three dimensional Poisson's equation, two dimensional Schrodinger equation on the cross section plane, and also transport equation. We have shown that for lengths smaller than 15 nm, short channel effects dominate. When the dimensions become smaller, interelectronic distance decreases and the interaction between electrons and also exchange correlation effects increase. We have also demonstrated that short channel effects are decreased using the device which has a good control of gate.

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