Performance evaluation of energy saving in core router architecture with Low Power Idle for OBS networks

Yang, Won-Hyuk; Jung, Jin-Hyo; Kim, Young-Chon

doi:10.1109/icoin.2012.6164417

Cited by 9 publications

(2 citation statements)

References 6 publications

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“…The buffer redundancy issue is solved by buffer shared router architecture and defect tolerant algorithm which increases the reliability of NoC and also it can reduce the power consumption as discussed in literature [7]. The core router architecture [8] is proposed with low power idle (LPI) to analyse energy saving effect on optical burst switching (OBS) networks which decreases consumption of energy at low offered load. A new pipelined router [9] is designed and focused only on router latency reduction, which decreases the latency and increases the router area.…”

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confidence: 99%

An efficient FPGA based NoC architecture for data communication

Jamagoud¹,

Bhairannawar²

2018

IJACR

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NoC is a new model in which a single silicon chip is utilized to execute various communication features used in substantial to huge scale integration systems. NoC is another change to the universe of systems and also the other way to deal with disadvantages like wiring delay. There are numerous types of interconnections like point-to-point, bus architecture, carbon nanotubes, optical fiber [1] where NoC perform is better to reduce the interconnection issues in future designs. System on chips designed using NoCs are getting popular in these days which provide solutions to the problem related to bus based designs and considered as the future of the application specific integrated circuit (ASIC) design [2]. NoC basically has three building blocks router, links and network adapter (NA) [3]. NoC approach has numerous benefits over traditional bus method and also provides high throughput as buses are less scalable and limited bandwidth [4].

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