Performance evaluation of cascadable built-in tester for large I/O multichip modules

Abstract

A Cascadable Built-In Tester (CBIT) for testing multichip modules (MCMs) with large number of VO pins is i n d u c e d . The CBIT can function both as a test pattem generator and as a signature analyzer. CBITs are cascadable to produce a maximal length pseudo-random sequence. This sequence yields high fault coverage due to the small signature aliasing probability and the uniqueness of the test patterns generated. A "pipelined test" concept is applied, which concurrently shares CBITs between multiple MCMs to reduce overall test time and area overhead. . lntroductiorl Current VLSI and WSI technologies strive to compact complex state machines on a single die or a wafer. The new packaging technology, multichip module (MCM) [3]. integrates several ICs on a substrate to minimize propagation delays and printed circuit board (PCB) complexity. As the complexity of the modules increases, more and more internal logic becomes unobservable due to the limitation of the pin count. Built-in tests are widely used to test complicated circuits thereby circumventing U0 pin limitations and facilitating intemal circuit access [9]. The basic concept of built-in tests is to integrate a testing suucture that performs test pattem generation and circuit verification of the modules, while minimizing test time and are-a overhead. Examples of well known built-in test methods are Scan design, Built-in Logic Block Observation (BILBO), etc [2].Scan design methods involve disconnecting the memory elements, the flip-flops, from the combinational logic. The main problem of the Scan methods is the overwhelming amount of test output generated by any relatively large circuit. One popular data compaction solution is signature analysis. which utilizes a Linear Feedback Shift Register (LFSR) to receive and modify the output data. The residue in the shift register, also called the signature. of a faulty circuit will differ from that of a good circuit after a long sequence of test patterns.BILBO is a technique that combines the basic features of scan design with those of signature analysis [6]. The original 8-bit BILBO design has not kept pace with the bandwidth of today's devices where internal VLSI bus paths have long since doubled from eight to 16 bits and again to 32 bits wide. Therefore, it is essential to redesign the BILBO circuitty to accommodate the wider bus path of today's complex VLSI devices. In [l], a family of concatenating polydividers with primitive characteristic polynomials wme proposed for packaged chips. In this paper we propose a cascadable built-in test smcture, called Cascadable Built-In Tester (CBIT) to be used as a library cell or macro in a standard cell design environment. CBIT is designed to implement the maximal length pseudo-random sequence for data width multiples of 8 bits to achieve high fault coverage. Fault coverage refers to the percentage of faults detected within the module being tested.In addition, the effectiveness of the built-in test strategy is evaluated by examining the total test time and area overhead needed f...