Performance evaluation of canny edge detection on a tiled multicore architecture

Abstract

In the last few years, a variety of multicore architectures have been used to parallelize image processing applications. In this paper, we focus on assessing the parallel speed-ups of different Canny edge detection parallelization strategies on the Tile64, a tiled multicore architecture developed by the Tilera Corporation. Included in these strategies are different ways Canny edge detection can be parallelized, as well as differences in data management. The two parallelization strategies examined were loop-level parallelism and domain decomposition. Loop-level parallelism is achieved through the use of OpenMP, 1 and it is capable of parallelization across the range of values over which a loop iterates. Domain decomposition is the process of breaking down an image into subimages, where each subimage is processed independently, in parallel. The results of the two strategies show that for the same number of threads, programmer implemented, domain decomposition exhibits higher speed-ups than the compiler managed, loop-level parallelism implemented with OpenMP.

Parallel Generation of Image Layers Constructed by Edge Detection Using Message Passing Interface

“…Several threshold techniques [9,10,11,12,13] have been implemented to adapt threshold values to produce high quality edges. Some studies discussed edge detection parallelization to increase the execution speedup [14,15,16,17 ].…”

Parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs

“…The CED included in the Intel OpenCV Libray [3] offers fast edge detection, but does not perform optimally in a noisy environment (see Fig. 1 CED was implemented on a Tilera processor in [10], using loop-level parallelism and domain decomposition. The results of [10] show that domain decomposition offers better scalability compared to loop-level parallelism.…”

“…1 CED was implemented on a Tilera processor in [10], using loop-level parallelism and domain decomposition. The results of [10] show that domain decomposition offers better scalability compared to loop-level parallelism. However, their implementation is restricted to the Tilera64 architecture, and results are shown for only eight cores out of sixty-four available.…”