Performance Evaluation of Bypassing Array Multiplier with Optimized Design

Abstract

In this paper a new method is proposed to reduce power and area of the array multiplier. In the proposed method vector merging final adder is removed at final stage of the multiplier, at the final stage the generated carry is given to the input of the column of top adder. The adders also do the same what the vector merging final adder can do. The method is applied for array multiplier and column bypassing multiplier (CBM). The results are carried out by H-Spice with different TSMC (Standard and PTM) technology files at a supply voltage 2.0V. Array multiplier has shown 13.91% and Proposed Column Bypassing Multiplier (PCBM) shown 23.38% less power consumption for 180nm CMOS technology than the conventional array multiplier and CBM. 14-T full adder is used to design the multipliers. Due to elimination of the final adder proposed method saves 56 transistors and cause low area. Embedded, DSP General Terms

Implementation of 4×4-Parallel-Multiplier using Modified Bypassing Architecture

“…Based on the concept of a low cost low-power Jin-Tai Yan bypassing based multiplier [2], [7], [8], modification further proposed. However, the introduction of the bypassing circuit for the control signal generation decreases the power dissipation and when compared with the referenced design, it provides good results as discussed in the later section.…”