Performance evaluation of a microprocessor with on-chip DRAM and high bandwidth internal bus

Iwata, S.; Shimizu, Toshihisa; Korematu, J.; Dosaka, K.; Tsubota, Hiroyuki; Saitoh, Kazunori

doi:10.1109/cicc.1996.511089

Cited by 13 publications

(4 citation statements)

References 2 publications

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“…One important conclusion from this is that, for these benchmarks, an IRAM implementation of a conventional architecture is not likely to lead to dramatic performance gains. This is consistent with other preliminary IRAM investigations [33][32] [22]. This illustrates the importance of investigating new performanceoriented architectural ideas and organizations that can take better advantage of the lower latency and dramatically higher bandwidth between the processor and memory that IRAM offers.…”

Section: Performancesupporting

confidence: 90%

“…In addition, Mitsubishi has announced the M32R/D, which integrates a proccssor, 2KB of SRAM cache, and 2 MB of DRAM and is targeted nt personal digital assistants [41] [22]. They state that integrating a processor with memory significantly reduces power dissipation, Researchers at Sun [40] evaluated the performance of a RISC processor on a 256 Mb DRAM, using the sense amps as caches, They arbitrarily limited their additions to be about 10% of the DRAM size, and found that they could achieve comparable integer performance and about half the floating point pcrformnncc compared to a 1995 DEC Alpha.…”

Section: Related Workmentioning

confidence: 99%

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The energy efficiency of IRAM architectures

Fromm

Perissakis

Cardwell

et al. 1997

Proceedings of the 24th Annual International Symposium on Computer Architecture

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Portable systems demand energy eflciency in order to maximize battery l&e. IRAM architectures, which combine DRAM anda processor on the same chip in a DRAMprocess, are more energy e$cient than conventional systems, The high density of DRAMpermits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAMmemory accesses to be satisfied on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which contribute significantly to the energy consumption ofa system. To quanhfy this advantage we apply models of energy consumption in DRAM and SRAMmemories to results from cache simulations of applications reflective of personal productivity tasks on low power systems. We find that #AMmemory hierarchies consume as little as 22% of the energy consumed by a conventional memory hierarchy for memoryintensive applications, while delivering comparable perJormance. Furthermore, the energy consumed by a system consisting of an IRAM memory hierarchy combined with an energy eficient CPU core is as little as 40% of that of the same CPU core with a traditional memory hierarchy.

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Section: Performancesupporting

confidence: 90%

Section: Related Workmentioning

confidence: 99%

The energy efficiency of IRAM architectures

Fromm

Perissakis

Cardwell

et al. 1997

Proceedings of the 24th Annual International Symposium on Computer Architecture

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“…A bus is composed of a set of nets that transfers information in parallel from one functional unit to others. Buses are widely used in computation and storage intensive designs like microprocessors [5]. The growing trend of Intellectual Property (IP) integration also involves an increasing portion of bus connections and bus interfacing.…”

Section: Introductionmentioning

confidence: 99%

Semi-detailed bus routing with variation reduction

Mo¹,

Brayton

2007

Proceedings of the 2007 International Symposium on Physical Design

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“…Buses are used widely in computation and storage intensive designs like microprocessors [5]. Bus routing techniques have been studied by various researchers.…”

Section: Introductionmentioning

confidence: 99%

A simultaneous bus orientation and bused pin flipping algorithm

Mo¹,

Brayton

2007

2007 IEEE/ACM International Conference on Computer-Aided Design

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-The orientation of a bus is defined as the direction from the Least Significant Bit (LSB) to the Most Significant Bit (MSB). Bused pin flipping is a property that allows several bused pins to flip without changing the system functionality. In this paper a simultaneous bus orientation and bused pin flipping algorithm is presented. The algorithm can be integrated into a bus-centric floorplanner targeting bus-rich designs such as microprocessors. Experimental results show that a floorplanner enhanced by the algorithm produces high quality floorplans in terms of bus routing.

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Performance evaluation of a microprocessor with on-chip DRAM and high bandwidth internal bus

Cited by 13 publications

References 2 publications

The energy efficiency of IRAM architectures

The energy efficiency of IRAM architectures

Semi-detailed bus routing with variation reduction

A simultaneous bus orientation and bused pin flipping algorithm

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