Performance Evaluation of 14 nm FinFET‐Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

Lim, Wei Hong; Chin, Huei Chaeng; Lim, Cheng Siong; Tan, Michael Loong Peng

doi:10.1155/2014/820763

Cited by 25 publications

(13 citation statements)

References 15 publications

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“…From Figure 6(a), the SNM of the 6T SRAM cell is 400mV. The value is better than the others work [5], [7], [8]. It verifies that FinFET based 6T SRAM has higher ability to retain stable data during standby mode operation.…”

Section: B Static Noise Margin (Snm) Of 22nm Finfet Based 6t Srammentioning

confidence: 74%

“…However, the 6T SRAM cell scheme faces the degradation of performance during the read operation. Therefore, another topology of 8T SRAM cell is proposed to solve the destructive read problem that occurs in the conventional 6T SRAM cell by separating the read and write operation [5][6][7][8]. The storage nodes of the 6T SRAM cell are used to store the logical values '0' and '1'.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

Alias¹,

Hamzah²,

Tan³

et al. 2019

EECSI

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The development of the nanotechnology leads to the shrinking of the size of the transistors to nanometer region. However, there are a lot of challenges due to size scaling of the transistors such as short channel effects (SCEs) and threshold voltage roll-off issues. Fin-Type Field Effect Transistor (FinFET) is another alternative technology to solve the issues of the conventional MOSFET and increase the performance of the Static Random Access Memory (SRAM) circuit design. FinFET based SRAMs are faster and more reliable which are often used as memory cache for high speed operation. However, 6T SRAM cell suffers from access transistor sizing conflict resulting in a trade-off between read and write stability. This paper presents an investigation of the stability performance in retention, read and write mode of 22nm FinFET based 8T SRAM cell. The performance comparison of 22nm FinFET based 6T and 8T SRAMs were made. The simulation of the SRAM model are carried out in GTS Framework TCAD tool based on 22nm technology. In 8T SRAM cell, two n-FinFETs are added to the conventional 6T SRAM cell which will be controlled by the Read Word Line (RWL) to isolate the read and write operation path for better read stability. FinFET based 8T SRAM cell gives better performance in Static Noise Margin (SNM) and power consumption than 6T SRAM cells. The simulation results affirms the proposed FinFET based 8T SRAM improved read static noise margin by 166.67% and power consumption by 76.13% as compared to the FinFET based 6T SRAM.

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Section: B Static Noise Margin (Snm) Of 22nm Finfet Based 6t Srammentioning

confidence: 74%

Section: Introductionmentioning

confidence: 99%

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

Alias¹,

Hamzah²,

Tan³

et al. 2019

EECSI

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“…FinFET is a multi-gate transistor and so because of the several gates acting on the channel, it has excellent electrostatic properties. Above all the beauty of MOSFET device "Scaling" exists in FinFET [2].…”

Section: Introductionmentioning

confidence: 99%

FinFET SRAM cell with improved stability and power for low power applications.

Birla

2019

JICS

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In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

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“…Almost, the aforementioned arithmetic operation can also be summed up as follows: addition, negative addition, repeated addition, and repeated negative addition. In the digital system, it's crucial to have a full adder that is low in power consumption, of high speed, power efficient, and secure [3]. Compared to conventional MOSFET technology, the brand new FinFET technology can be applied in 1-bit full adder, to prolong silicon downscaling and increase the device efficiency and power efficiency of full adder.…”

Section: Introductionmentioning

confidence: 99%

Finfet Based 16 Bit Alu Units for Leakage Reduction

Chandrakant¹

2016

IJRET

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An Arithmetic Logic Unit (ALU) acts as a heart for all microprocessors. It performs logical or arithmetic operations. It's getting smaller and more complicated in recent days to enable the progress of extra powerful however smaller design. However, there are just a few limiting reasons that slow down the growth of smaller and additional problematic chip when CMOS is used. The foremost boundaries in scaling the bulk CMOS are quick channel effects, sub-threshold leakage and gate-dielectric leakage. FinFET has an excellent control on short channel results within the sub-micron regime hence developing the probability to scale the transistor. Because of this cause, the small size transistor can have a higher intrinsic gain and less off-state current in comparison with the bulk counterpart. 16-bit ALU that performs basic logical, arithmetic, and shifting operations has been designed using FinFET constructions and leakage power has been studied and compared with the MOSFET structure.

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Performance Evaluation of 14 nm FinFET‐Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

Cited by 25 publications

References 15 publications

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

FinFET SRAM cell with improved stability and power for low power applications.

Finfet Based 16 Bit Alu Units for Leakage Reduction

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