Performance enhancement and area optimization of 3×3 NoC using random arbiter

Abstract

Network-on-Chip (NoC) is a new approach for designing the communication subsystem among IP cores in aSystem-on-Chip (SoC). NoC applies networking theory and related methods to on-chip communication and brings out notable improvements over conventional bus and crossbar interconnections. NoC offers a great improvement over the issues like scalability, productivity, power efficiency and signal integrity challenges of complex SoC design. In a NoC, the communication among different nodes is achieved by routing packets through a pre-designed network according to different routing algorithms. Therefore, architecture and related routing algorithm plays an important role to the improvement of overall performance of a NoC. The technique one which is used presently in node is priority based technique packet routing which leads the packet stacking which intern leads to performance degradation. In this paper, proposes a modified random Arbiter combined with deterministic XY routing algorithm to be used on router of NoC. In this method router contains random arbiter along with priority encoder which results into fast way to transfer packet via a specific path between the nodes of the network without stacking. This in turn optimizes the packet storage area and avoids collision because node arbiter will service the packets randomly without any priority. In addition to that this method will ensure a packet always reaches the destination through the possible shortest path without deadlock and livelock.

Design and implementation of crossbar scheduler for system‐on‐chip network in quantum dot cellular automata technology

“…Several techniques have been proposed and implemented to reduce the area and latency of the on‐chip network. These methodologies were suitable for implementation using silicon‐based CMOS technology.…”