Performance Enhanced 6-bit Phase Shifter in 65-nm CMOS Technology

Study and analysis of a QFN packaged 8-bit Phase shifter design using 65-nm CMOS technology

“…The topologies of switch designs studied are given in Figure 2. The variation in the insertion loss and phase over the band of 3 -4 GHz is as shown in Figure 3 and Figure 4 respectively [11].…”

“…This design is aimed for integration into T/R core chip. An accurate performance enhanced switched line topology based phase shifter in S-band using 65-nm CMOS technology is given in [11]. The RMS phase errors is < 1 • and 2 • for the normalized bandwidth and an insertion loss <14 dB is achieved which is compensated using an on wafer designed LNA.…”