Performance-driven dynamic thermal management of MPSoC based on task rescheduling

Ganeshpure, Kunal; Kundu, Sandip

doi:10.1145/2566661

Cited by 7 publications

(5 citation statements)

References 32 publications

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“…A spatial thermal management scheme to reduce the temperature of FPGAs by scheduling high power consumption tasks on cooler processing elements is discussed in [84]. [85] shows a dynamic rescheduling technique for thermal management of MPSoCs. [86] discusses DVFS and scheduling-based dynamic power and thermal management for NoC-Based Heterogeneous MP-SoCs.…”

Section: Prevalent Power Thermal and Fault Management Methodsmentioning

confidence: 99%

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

Sharma

2024

Preprint

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<p>Embedded systems for application domains like robotics, aerospace, defense, etc. nowadays are developed on System-on-Chip (SoC) platforms based on Field Programmable Gate Array (FPGA) devices to support computation-intensive multi-task multi-modal dynamic workloads common for these applications. These systems therefore face the challenge to sustain the performance of their dynamic workloads in presence of variations in power budget, die temperature, and/or occurrence of hardware faults. This work proposes Run-time Structural Adaptation (RTSA) as a mechanism for mitigating these factors. One of the major contributions of this work is creation of a run-time decision-making method, ‚ÄúExplorer‚Äù, to carry out RTSA for FPGA-based SoCs and mitigate variations in the internal and external factors simultaneously. Whenever there is a change in the system‚Äôs set of constraints, Explorer selects an appropriate variant of hardware processing circuit for each active task from a large design space to form a system conÔ¨Åguration that satisÔ¨Åes each task‚Äôs performance speciÔ¨Åcation and all other system constraints. To support the practical deployment of Explorer, this work presents a method to derive run-time power consumption and die temperature estimation models for any FPGA-based device. This novel methodology of model derivation based on the FPGA platform and application running on it is another contribution of this work. The model derivation methods are formulated after detailed experimental analysis of power consumption and thermal behaviors of recent FPGA devices. Explorer can evaluate potential system conÔ¨Ågurations using the derived models to select a suitable system conÔ¨Åguration for RTSA. Experimental implementation of Explorer on the Zynq XC7Z020 SoC shows worst case execution time of 130 us, which demonstrates its suitability for RTSA for most applications associated with multi-stream computation-intensive tasks. This work also proposes an approach for automating model derivation which helps systems self-derive their model coefficients during system production and re-derive them due to changes in system platform, application, and/or environmental conditions. This significantly reduces model derivation time while avoiding any human involvement. This work thus presents the methods and models necessary to enable real systems utilizing FPGA devices to carry out RTSA and sustain their dynamic workloads amid dynamic environmental and hardware resource constraints.</p>

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Section: Prevalent Power Thermal and Fault Management Methodsmentioning

confidence: 99%

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

Sharma

2024

Preprint

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“…A look into the present-day research efforts shows that there are several methods used for run-time adaptation to different parameters. Methods such as power gating [21,22], Dynamic Voltage and Frequency Scaling (DVFS) and DFS [23][24][25][26], dynamic scheduling techniques [25,[27][28][29][30] and dynamic mapping techniques [25,[31][32][33], and dynamic task migration are used for power and/or thermal aware workload management. Methods such as Triple Modular Redundancy (TMR) and scrubbing [34][35][36], Built-in Self-Test (BIST) procedures [37], device reprogramming to avoid damaged regions [38], dynamic scheduling and mapping [39][40][41], run-time relocation based methods [42,43], and variant-based methods [44][45][46][47] are commonly used methods for fault management.…”

Section: Literature Reviewmentioning

confidence: 99%

A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations

Sharma

Kirischian

2021

International Journal of Reconfigurable Computing

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One of the growing areas of application of embedded systems in robotics, aerospace, military, etc. is autonomous mobile systems. Usually, such embedded systems have multitask multimodal workloads. These systems must sustain the required performance of their dynamic workloads in presence of varying power budget due to rechargeable power sources, varying die temperature due to varying workloads and/or external temperature, and varying hardware resources due to occurrence of hardware faults. This paper proposes a run-time decision-making method, called Decision Space Explorer, for FPGA-based Systems-on-Chip (SoCs) to support changing workload requirements while simultaneously mitigating unpredictable variations in power budget, die temperature, and hardware resource constraints. It is based on the concept of Run-Time Structural Adaptation (RTSA); whenever there is a change in a system’s set of constraints, Explorer selects a suitable hardware processing circuit for each active task at an appropriate operating frequency such that all the constraints are satisfied. Explorer has been experimentally deployed on the ARM Cortex-A9 core of Xilinx Zynq XC7Z020 SoC. Its worst-case decision-making time for different scenarios ranges from tens to hundreds of microseconds. Explorer is thus suitable for enabling RTSA in systems where specifications of multiple objectives must be maintained simultaneously, making them self-sustainable.

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“…Methods like Dynamic Voltage and Frequency Scaling (DVFS) and DFS are used to control power consumption [25,26] and temperature [27] and also to sustain task performances in presence of temperature variations [28]. Dynamic scheduling techniques [27,[29][30][31][32] and dynamic mapping (or resource management) techniques [27,[33][34][35] are other methods used to achieve power and/or thermal aware workload management. Dynamic scheduling and mapping techniques are also employed for fault mitigation [15,36,37].…”

Section: Literature Reviewmentioning

confidence: 99%

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Sharma¹,

Kirischian²,

Kirischian³

2021

Preprint

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Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

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Performance-driven dynamic thermal management of MPSoC based on task rescheduling

Cited by 7 publications

References 32 publications

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

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