Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node

Abstract

Applications of stress/strain are now part of technology 'boosters' in microelectronics industry among other technologies such as silicon-on-insulator or the metal gate/high-k techniques. Application of strain in channel significantly increases carrier mobility. Thus, there is a need to characterize the deformations at nanoscale in the semiconductor induced by the strain. Uniaxial compressive strain has been an indispensable performance booster for p-channel FinFETs. In this work, based on extensive 3D process and device simulations with mechanical stress simulations using finite element techniques, performance assessment of nanoscale trigate FinFETs with uniaxially strained-SiGe channel (fin) has been presented. A comprehensive study based on stress tuning parameters is carried out to investigate the possible highest amount of process induced stress transfer to SiGe fin for optimization of device performance. The impact of process-induced strain on carrier mobility enhancement in 7 nm technology node is another major focus of this study. The stress transfer efficiency is shown for different process conditions with different Ge content. Technology CAD simulations show that strain in the fin is larger for higher Ge contents in the SiGe layer for p-channel FinFETs. For the first time, conversion from biaxial compressive strain of SiGe to uniaxial compressive strain in SiGe layers via process simulation has been demonstrated and implemented in the virtual fabrication of uniaxially strained-SiGe channel (fin) tri-gate FinFETs. A detailed performance comparison has been performed with conventional bulk-Si tri-gate FinFETs.

Design and optimization of stress/strain in GAA nanosheet FETs for improved FOMs at sub-7 nm nodes

“…So, the slope of the transfer characteristics curve decreases and hence threshold voltage decreases. This is true even when stress is not introduced in the devices [41]. Moreover, the lowering stress increases the bandgap or vice versa and with the increase in stress, the bandgap decreases.…”

“…It has been observed that the carriers are dispersed more evenly among the sub-valleys, which is the primary factor in improving mobility. The stress-induced hole mobility enhancement can be given by [41]…”

“…In figure 5(b), it can be observed that the longitudinal stress along each stack of strained-SiGe NSFETs is different. The SiGe layer is pseudomorphically grown over Si [41,43]. After patterning and etching steps defining the sheet width, the SiGe sheets in the structure are partially relaxed.…”

Atomic‐scale strain analysis for advanced Si/SiGe heterostructure by using transmission electron microscopy

“…On the other hand, multiple experiments or measurements can be performed, increasing the reliability of the data processing. In addition, simulated data based on a finite element model can be created to validate the accuracy of the data processing methods 136 …”

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

“…In this regard, strained silicon, III-V materials, and germanium (Ge) are suggested as the future channel material as these provide higher electron mobility compared to silicon. [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] Out of these non-silicon materials, Ge graves the highest attention of device researchers due to its exceptionally high hole mobility. [17][18][19][20][21] As the current technology deals with CMOS architecture, we need both NMOS and PMOS to be implemented.…”