Performance Comparison of FPGA-based Methods for Preamble Detection at Interference

Hardware design for data synchronization under high interference

“…So, the preamble used for the implementation and the post implementation simulations of the design was constructed by aligning 16 10-bit 1111100000 building blocks and its general form is 111110000011111000001111100000……. Considering the frequency table, the probability of a random perfect compatibility is (10 -5 ) 16 . This is the error without BER which is negligible.…”

“…Adding the values in Table IV for compatibilities greater than or equal to 8 bit we end up with 0.017 (cumulative probability). This needs to be replicated 16 times in a row for 80% so the total chance of such an event is (0.017) 16 , which is an extremely unlikely scenario.…”

“…Fortunately, because of the nature of our design and the setting of the preamble, this problem is solved by default. As mentioned in the preamble section, the chance of a 160-bit sequence having an 80% compatibility (128 same bits) with the preamble is (0.017) 16 . This percentage of miss detections is negligible.…”

“…The design was implemented on the FPGA board KCU116 [14] which houses the GTY transceivers [15]. The entire design was inspired by the techniques used in OFDM synchronization [16] where preambles are used to detect symbols [17]. The main difference between these designs and our proposal is the fact that the OFDM synchronization circuits accept signal samples of various bit accuracies (8-bit,16-bit) while the input of our design is a binary data stream.…”

High throughput bit pattern matching implemented on FPGA

“…In both the platform of implementation is the kcu 116 ultrascale+ FPGA. A major inspiration for the form of circuit has been the symbol detectors for OFDM synchronization [1].…”