Performance Comparison of AMBA Bus-Based System-On-Chip Communication Protocol

Shrivastav, Anurag; Tomar, Geetam Singh; Singh, Ashutosh Kumar

doi:10.1109/csnt.2011.98

Cited by 41 publications

(9 citation statements)

References 3 publications

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“…To move streams in and out of the shared memory, a DMA engine can be used. For this reason, we used AXI Direct Memory Access (DMA) IPs ( Figure 5), which provide a direct memory access of a high bandwidth between the AXI4-Stream IP and AXI4 memory mapped interfaces [19]. Researchers have reported that, at a clock frequency of 100 MHz, data transitions may be established from both AXI4 master and AXI-Stream slave to AXI4 master at a data rate of 400 MBps and 300 MBps, respectively, being a quota of the theoretical bandwidths of 99.76% and 74.64%.…”

Section: Fpga Bitstreammentioning

confidence: 99%

A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Tsiktsiris

Ziouzios

Dasygenis³

2018

Technologies

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Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided.

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Section: Fpga Bitstreammentioning

confidence: 99%

A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Tsiktsiris

Ziouzios

Dasygenis³

2018

Technologies

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“…Access to the target device is controlled through a MUX, there by admitting bus-access to only one master at a time. AHB bus integrates high performance modules like processors (ARM, DSP, AVR) and memories [7].…”

Section: Multi Processor System-on-chip (Mpsoc)mentioning

confidence: 99%

“…Data can be transferred using write and read data channels between master and slave. The write transactions involve all the data in the direction from the master to the slave.AXI protocol has an additional write response channel for indication to the master, the completion of the write transaction by the slave [7].…”

Section: Advanced Extensible Interface (Axi3)mentioning

confidence: 99%

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A Frame work on AMBA Bus based Communication Architecture to Improve the Real Time Computing Performance in MPSoC

VenkateswaraRao¹,

Krishna²,

Yasaswini³

2014

IJCA

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Enormous advancements in System-on-Chip (SoC) have led to a new area called as MPSoC, having single chip with many processors. MPSoC is usually targeted for high-end embedded designs to meet real-time requirements, where performance and bandwidth plays a major role. Multi Processor Systemon-Chip (MPSoC) deals with multiple on-chip processors and processing elements that are essential for multi-core processors integrated onto the single chip. As more and more processors are integrated onto the same silicon chip, there should be proper communication and synchronization to ensure better performance. For this purpose, several Communication Architectures (CAs) have been developed like ARM AMBA, IBM Core Connect, Altera Avalon, and Open Cores Wishbone. One of the major challenges is to select a suitable architecture among the various MPSoC architectures. AMBA bus is widely used in the highperformance and high frequency SoC designs. This paper deals with several topologies and communication protocols. In this paper AMBA versions and their buses/interfaces are discussed.

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“…The most important issue in a SoC these days is not only the housing of components or blocks but also the way these are interconnected. AMBA provides an efficient solution for the blocks to interface with each other [19]. AMBA (shown in Fig.…”

Section: Ambamentioning

confidence: 99%