Abstract:We present a highly reliable Flash based FPGA fabricated with a 65nm embedded process. A very robust ON and OFF Vt window, over 8V, has been achieved with tight cell to cell distributions. 1k program/erase cycles have been performed and charge trap induced Vt window loss is less than 0.2V. Some initial Vt shift is seen at erase side after retention bake. The shift saturates after 24 hours and the post-bake Vt window is close to 8V. There is still a 2V margin from our design spec which is 6V. Operation disturb … Show more
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