Performance and characteristic analysis of double gate MOSFET over single gate MOSFET

Monisha, A.; Rao, R. Sambasiva

doi:10.1109/ecs.2014.6892627

Cited by 5 publications

(1 citation statement)

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“…Every two years the number of transistors doubles because the size of the MOSFET is reduced. oxide semiconductor field effective transistor (MOSFET) is a semiconductor device used in various applicationslike for analog and RF applications to handle the radio frequency signals that are high in power from devices like television, radio transmitter, amplifiers [2].For reduction in cost and to increase the speed of the device double gate MOSFETs are taken into consideration [3]. MOSFET's are used for biomedical applications that are used as a biosensor to detect biomolecules like enzymes, nucleotide, protein, and antibodies [4] [5].…”

Section: Introductionmentioning

confidence: 99%

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

Mendiratta

Tripathi

2021

Silicon

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In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x 10 −6 A/μm with reduced OFF-state leakage current up to1.37 x 10 −17 A/μm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 K and 400 K shows a small variation in OFF-state current (<15%). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All the design and analysis has been done with a 2D/3D Visual TCAD device simulator.

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Section: Introductionmentioning

confidence: 99%