Performance analysis through memory of a proposed parallel architecture for the efficient use of memory in image processing applications

Abstract

This paper presents an analytical method to measure the performance through memory of a proposed parallel processing computer architecture for image processing applications. We developed an analytical model of our proposed architecture and a conventional architecture with respect to the system's local and main memory to measure and compare the performances of these two systems. From our model we can evaluate the performance of the proposed architecture in terms of processor utilization, number of busy memory modules and the fraction of the programs data structure resident in local memory. The main idea behind our proposed architecture is to carry out image processing work in a highly parallel manner so that the response time is shorter. The proposed architecture keeps both the processor and the memory system as busy as possible in order to obtain faster response time and proper utilization of the hardware compared to a conventional parallel processing architecture. Our proposed architecture consists of an array of processing elements(PEs), a system control unit(SCU), interconnection network and memory modules. Each PE contains two central processing units(CPU), one is responsible for the execution of all non-memory operations and the other is responsible for all memory operations. The overall response time of a job is faster because we divide the actual execution and the memory operation into two separate entities and carry them out concurrently. We also present an image processing algorithm suitable for the proposed architecture and analyze their performance compared to the conventional system.

Low power memory storage and transfer organization for the MPEG-4 full pel motion estimation on a multimedia processor

“…Many software-oriented memory management approaches exist in literature but they do not focus on the combination of performance and overall power, which is vital as motivated above. Several papers have analyzed memory organization issues in processors, like the processor and memory utilization [17], [36]. This is however only seldomly resulting in a formalizable method to guide the memory organization issues.…”