Performance Analysis of Prefetching Thread for Linked Data Structure in CMPs

Abstract

Chip Multiprocessor (CMP) presents new opportunities to data prefetching. Prefetching thread is a well known approach to reduce memory latency and to improve performance, and has been explored in different applications. However, for applications with linked data structure(LDS), prefetching thread tends to achieve little overall performance gains. In this paper, we analyze the performance of conventional prefetching thread by an example and five selected benchmarks from Olden benchmark suite. The experimental results show that it gets best performance when computation/access latency ratio is close to 1. In addition, we propose a theorem with its proof and testify it by our experiment results.

The Performance Optimization of Threaded Prefetching for Linked Data Structures

“…To deal with irregular access patterns that are hard to predict, helper thread based prefetching techniques have been proposed [18][19][20][21][22][23][24][25][26][27]. Helper threaded prefetching is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread.…”

“…As indicated in [20,21], the characteristics of operations in hotspot affect the performance of the helper thread. Hence, we define Computation/Access Latency Ratio (CALR), which is the result of cycles in computation divided by cycles in memory accesses.…”

Estimating Effective Prefetch Distance in Threaded Prefetching for Linked Data Structures

“…To tolerate memory access latency, there have been a plethora of proposals for data prefetching [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Data prefetching techniques improve performance by predicting future memory accesses and fetch them in cache before they are accessed.…”

“…Helper thread based prefetching techniques [19][20][21][22][23][24][25][26][27] are promising methods to deal with irregular access patterns that are hard to predict. However, because LDS are traversed in a way that prevents individual accesses from being overlapped, conventional helper thread based prefetching techniques have some problems with LDS programs.…”

“…With the advent of chip multiprocessors (CMP) architectures, thread-based prefetching and speculative execution techniques [9][10][11][12][13][14][15][16][17][18][19][20] utilizes a helper thread to boost the performance of main thread by prefetching data into cache. Helper thread based prefetching techniques [19][20][21][22][23][24][25][26][27] are promising methods to deal with irregular access patterns that are hard to predict.…”