Performance analysis of large multicast packet switches with multiple input queues and gathered traffic

Zhu, Weiying; Song, Min

doi:10.1016/j.comcom.2009.12.003

Cited by 7 publications

(5 citation statements)

References 24 publications

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“…Consequently, multicast queuing structure can vary from just one multicast (first in first out) FIFO queue per input to 2 1 N queues per input, where N is the number of output ports of the switch, and considerable amount of solutions based on the architecture have therefore been proposed such as [3][4][5][6][7][8]. The performance of such queuing structure was analyzed in [9][10][11]. Depending on the above input queuing structure, integrated scheduling algorithms have been proposed.…”

Section: Introductionmentioning

confidence: 99%

Integration of Unicast and Multicast Scheduling in Input-Queued Packet Switches with High Scalability

Jiang

Qiu²,

Zhang³

et al. 2012

JSCSE

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This paper focuses on the scalability problems for high-speed switches, and presents an integrated scheduling algorithm that supports unicast and multicast traffic efficiently in input-queued packet switches. Considering the tradeoff balancing complexity and performance, the proposed integrated algorithm performs without iteration, and reduces the scheduling overhead to O(N) with a two-phase (request-grant) sequential scheduling for unicast and multicast traffic. In addition, it can be implemented in a fully distributed way, which is more suitable for high-speed switches. Simulation results show that the proposed algorithm exhibits a good performance in terms of throughput and average delay, at different traffic compositions under various traffic patterns

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Section: Introductionmentioning

confidence: 99%

Integration of Unicast and Multicast Scheduling in Input-Queued Packet Switches with High Scalability

Jiang

Qiu²,

Zhang³

et al. 2012

JSCSE

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show abstract

“…Whereas the other algorithms [1], [3] considered a circumscribed number of FIFO queues is maintained at each input to reduce the HOL blocking problem. Thus queuing architecture is denominated as k-MC-VOQ and performance of these multicast switches are analyzed theoretically [12], [15]. As the link speed grows dramatically, high speed switches will have less time to perform scheduling process.…”

Section: Fig1 Multicast Traffic Support In Core Routersmentioning

confidence: 99%

Multicast Due Date Round-Robin Scheduling Algorithm for Input-Queued Switches

Navaz¹,

Balasubramanian²

2016

IJCNIS

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Abstract-In recent years, the Internet has incremented the several incipient applications that rely on multicast transmission. This paper discusses the challenges of scheduling algorithms for multicast in high-speed switches that reduces the overhead of adaptation by selecting a HOL (Head of Line Cell) using Round Robin pointer. The objective of this paper is to design a scheduling algorithm called MDDR (Multicast Due Date Round-Robin) scheduling to achieve maximum throughput and low delay that has two phases request and grant. In request phase, MDDR assigns a Due Date (Request Time Slot) for HOL cells of each queue in the input port. Round Robin Pointer is utilized in the grant phase to select a request if HOL occurs. MDDR achieves more preponderant performance than MDRR (Multicast Dual Round-Robin), since the request shall be made when the Due Date is reached. MDDR mainly minimizes many requests made for output ports and time complexity. The simulation results show that the proposed algorithm has good switching performance in throughput and average time delay under Bernoulli and bursty traffic conditions.

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“…In general, they can be divided into two categories based on the type of switches adopted: Multicast scheduling for electronic switches, see, for example, [6], [7], [8], [9], [10], [11], [12], [13], [14], and multicast scheduling for optical switches, such as [15], [16], [17], [18]. Most multicast scheduling algorithms for electronic switches adopt the input queued (IQ) switching architecture, due to the fact that the internal bandwidth of IQ switch only needs to be as fast as the link rate, which is very promising for large routers and switches with very high port speed.…”

mentioning

confidence: 99%

“…Most multicast scheduling algorithms for electronic switches adopt the input queued (IQ) switching architecture, due to the fact that the internal bandwidth of IQ switch only needs to be as fast as the link rate, which is very promising for large routers and switches with very high port speed. To reduce Head-of-Line (HOL) blocking, i.e., packets behind the HOL packet in an input queue cannot be scheduled because the HOL packet is blocked, virtual output queues (VOQs) are usually adopted in many multicast scheduling algorithms for IQ switches [7], [8], [9], [10], [11], 12]. In [7], a novel virtual output queuing scheme was proposed for an N Â N switch, in which a shared data queue buffering packet contents and N VOQs buffering address information are placed at each input port.…”

mentioning

confidence: 99%

High-Speed Multicast Scheduling in Hybrid Optical Packet Switches with Guaranteed Latency

Zeng

Yang

2013

IEEE Trans. Comput.

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In this paper, we study multicast scheduling in the OpCut switch, a recently proposed hybrid optical/electronic switching architecture for transmitting high-volume traffic in core networks and parallel computers. First, we present a multicast scheduling algorithm called Guaranteed Latency Multicast Scheduling (GLMS) that considers the schedule of each packet for multiple time slots. We show that GLMS has several desirable features, such as guaranteed latency for all transmitted packets and adaptivity to transmission requirements. To relax the time constraint on computing a schedule, we further propose a parallel and pipeline processing architecture for GLMS that distributes the scheduling task to multiple pipelined processing stages, with N processors in each stage, where N is the switch size. Finally, by implementing it with simple combination logic circuits, we show that each processor can finish the scheduling for one time slot in Oð1Þ time complexity. We evaluate the performance of GLMS extensively against statistical traffic models and real Internet traffic, and the results show that the proposed GLMS algorithm can achieve very low average packet latency with minimum packet drop ratio.

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Performance analysis of large multicast packet switches with multiple input queues and gathered traffic

Cited by 7 publications

References 24 publications

Integration of Unicast and Multicast Scheduling in Input-Queued Packet Switches with High Scalability

Integration of Unicast and Multicast Scheduling in Input-Queued Packet Switches with High Scalability

Multicast Due Date Round-Robin Scheduling Algorithm for Input-Queued Switches

High-Speed Multicast Scheduling in Hybrid Optical Packet Switches with Guaranteed Latency

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