Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture

Khan, Zahid A.; Arslan, Tughrul; Erdogan, A.T.; Khawam, S.; Nousias, I.; Milward, M.

doi:10.1109/socc.2007.4545443

Cited by 1 publication

(1 citation statement)

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“…The near Shannon Limit performance [3] and high degree of parallelizable structure [4] of the code makes it most suitable for implementation in high data rate applications such as WLAN, WiMax, DVB-S2 and optical communication [5]. Hence, analyzing the performance and complexity of LDPC decoders is of paramount interest to communication engineers and researchers [6]. The performance of a LDPC decoder predominantly depends on the complexity of the underlying algorithm.…”

Section: Introductionmentioning

confidence: 99%

Analysis of performance and implementation complexity of simplified algorithms for decoding Low-Density Parity-Check codes

Chandrasetty

Aziz

2010

2010 IEEE Globecom Workshops

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This paper presents a novel technique to significantly reduce the implementation complexity of Low-Density ParityCheck (LDPC) decoders. The proposed technique uses high precision soft messages at the variable nodes but scales down the extrinsic message length, which reduces the number of interconnections between variable and check nodes. It also simplifies the check node operation. The effect on performance and complexity of the decoders due to such simplification is analyzed. A prototype model of the proposed decoders compliant with the WiMax application standard has been implemented and tested on Xilinx Virtex 5 FPGA. The implementation results show that the proposed decoders can achieve significant reduction in hardware complexity with comparable decoding performance to that of Min-Sum algorithm based decoders. The proposed decoders are estimated to achieve an average throughput in the range of 6 -11 Gbps, even with short code lengths.

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Section: Introductionmentioning

confidence: 99%