Performance Analysis of Gate All Around TFETs for Low Power Circuits

Abstract

On scaling down MOSFETs below 20 nm or so, it introduces several problems such as drain induced barrier lowering, high OFF-state current due to thinning of gate oxide, and other effects generally known as short channel effects. Keeping these faults into considerations, the market has evolved around several MOSFET like devices including Tunnel-field-effect transistors (TFETs). TFETs has significantly emerged as the substitute to MOSFETs. The TFET belongs to so-called steep-slope devices family because of its ability of scaling down the threshold voltage and VDD beyond the limits of basic CMOS. In this work we investigate the constant current mirror circuit level performance of gate-all-around TFETs and comparison has been drawn with the conventional MOSFET circuit. It is observed that TFET based current mirror circuit outperforms MOSFET based circuit. Therefore, TFETs can be utilized as a better candidate instead of MOSFET for low power circuit designing.