Performance Analysis of GaAs DG-JLMOSFET: Impact of Gate Oxide and Its Thickness

Choudhury, Parag; Bhuiyan, Reaz Uddin; Hasan, Md. Soyaeb; Sultana, Sunjida; Minim, Nawara Tanzee; Ahmed, Nafisa; Hasan, Md. Tanvir; Islam, Md. Rafiqul

doi:10.1109/tensymp54529.2022.9864435

Cited by 6 publications

(1 citation statement)

References 16 publications

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“…Due to its junction-free construction, it may be made in fewer steps, thermal efficiency, and resistance to SCEs. [1][2][3][4][5][6][7][8] Junctionless transistors have improved subthreshold slope (SS) and drain-induced barrier lowering (DIBL) in contrast to any traditional MOSFET, which has enhanced junctionless device performance.…”

Section: Introductionmentioning

confidence: 99%

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Abrishami

Orouji

2023

Physica Status Solidi (a)

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This work presents a double‐gate junctionless metal‐oxide field‐effect transistor (JLT) in a 20 nm regime by modifying central potential. In the proposed device, the off‐state current is reduced due to modifying the potential in the middle of the channel. The proposed structure is called as a modified central potential junctionless transistor (MCP‐JLT). The suggested device embeds two dielectric pockets (DPs) into the middle of the channel. The proposed technique has several effects on the proposed structure. Also, the impact of the DPs into the channel on the performance device is discussed. The proposed MCP‐JLT structure decreases the off‐state current (IOFF) by three orders of magnitude; besides, it can suppress the lateral electric field and also slightly reduces the drive current (ION), and reduces subthreshold swing (SS) compared to a typical junctionless FET (C‐JLT). Furthermore, the effect of the gate insulator materials on the proposed device's performance is discussed.

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