Performance analysis of double digit decimal multiplier on various FPGA logic families

James, Rekha K.; Jacob, K. Poulose; Sasi, Sreela

doi:10.1109/spl.2009.4914895

Cited by 9 publications

(6 citation statements)

References 6 publications

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“…The hardware implementation of decimal arithmetic is becoming a topic of interest to the researchers, for wide application of such arithmetic in the field of human-centric applications [1][2][3], where exact results are required. Generally, computer algorithms and architectures are based on binary number systems, because, of their simplicity from its counterpart i.e.…”

Section: Introductionmentioning

confidence: 99%

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications

Saha

Kumar

Bhattacharyya

et al. 2013

2013 International Symposium on Electronic System Design

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Vedic mathematics, is an ancient methodology, has a unique mathematical computation technique based on 16 sutras (formulae). High speed reciprocal unit based on such ancient mathematics is reported in this paper. Implementation methodology was adopted through sahayaks (auxiliary fraction) taken from such ancient mathematics and prototype was designed for practical signal processing applications. On account of the Vedic formulae, reciprocal approximation of a numbers is generated in fewer steps compared to Newton-Raphson's iteration based implementation with appreciable error in accuracy (~0.09%), offer high speed operation. The functionality of the algorithm was checked, and performance parameters like propagation delay, dynamic switching power consumption were calculated through spice spectre using 90nm CMOS technology. The propagation delay of the resulting 5-digit reciprocal unit was only ~3.57uS and consumes ~30.8mW power. The implementation methodology offered substantial reduction of propagation delay, and dynamic switching power consumption from earlier reported Newton-Raphson (NR) based implementation.

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Section: Introductionmentioning

confidence: 99%

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications

Saha

Kumar

Bhattacharyya

et al. 2013

2013 International Symposium on Electronic System Design

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“…Percentage of error is equal to: Computational error, E r , can be minimized if 3 ) is added to or subtracted from the approximated result. The comparison chart based on the proposed methodology is given in Figure 7.…”

Section: Error Analysismentioning

confidence: 99%

“…Thereby, hardware implementation of Applying Speci c Integrated Circuits (ASICs) has gained popularity during the last decade [1][2][3][4][5]. Generally, hardware implementation of the computer arithmetic circuits is based on binary number systems due to simplicity of operations from decimal number systems [6].…”

Section: Introductionmentioning

confidence: 99%

A new algorithm for the computation of the decimals of the inverse

Saha

Kumar

2017

Scientia Iranica

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Abstract. Ancient mathematical formulae can be directly applied to the optimization of the algebraic computation. A new algorithm used to compute decimals of the inverse based on such ancient mathematics is reported in this paper. Sahayaks (auxiliary fraction) sutra has been used for the hardware implementation of the decimals of the inverse. On account of the ancient formulae, reciprocal approximation of numbers can generate \on the y" either the rst exact n decimal of inverse, n being either arbitrary large or at least 6 in almost all cases. The reported algorithm has been implemented, and functionality has been checked in T-Spice. Performance parameters, like propagation delay and dynamic switching power consumptions, are calculated through spice-spectre of 90 nm CMOS technology. The propagation delay of the resulting 4-digit reciprocal approximation algorithm was only 1:8 uS and consumed 24:7 mW power. The implementation methodology o ered substantial reduction of propagation delay and dynamic switching power consumption from its counterpart (NR) based implementation.

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“…However, our target implementation platform is Application Specific Circuits (ASIC). Researchers in [18,19] proposed double digit decimal multipliers that can be used in floating point multiplier circuits. But our goal is to implement a high-speed one digit decimal multiplier.…”

Section: Survey Of Bcd Digit Multipliermentioning

confidence: 99%