Performance Analysis of Channel Estimator with Interference Detection Architecture

Abstract

The evaluation of the wireless channel linking a transmitter and a receiver is essential in many applications. In receiver design, channel estimate is a fundamental and difficult problem. A recent mathematical theory called compressive sensing (CS) makes use of the idea of randomness in the signal to recover sparse or compressible signals. This research work also proposes an efficient channel estimator with interference detection architecture for Multiple Input Multiple Output- Orthogonal Frequency Division Multiplexing (MIMO - OFDM) method. The proposed interference finding architecture efficiently detects and removes the interference between received signals with low power consumption and current consumption with minimum hardware requirements. The power consumption and latency for Virtex Family devices are 19mW and 9 ns respectively. The channel estimator with interference detection architecture is used to achieve the power consumption and latency (CPLD Family devices) are 21.97 and 10.32.