Performance analysis of buffered banyan networks under nonuniform traffic

Kim, Young Man; Lee, Kyungsook Y.

doi:10.1145/318789.318893

Cited by 8 publications

(3 citation statements)

References 11 publications

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“…On the flow control part, we address the inherent performance limitations of multi-stage networks with shallow buffers [3]- [6] using an hybrid, end-to-end scheduling scheme that combines prescheduled packet injections with unscheduled eager injections. We employ prescheduling because it can mitigate the contention within the fabric, and thus reduce the performance (throughput) losses caused due to blocking.…”

Section: Contribution and Related Workmentioning

confidence: 99%

Towards low-cost high-performance all-optical interconnection networks

Chrysos

Minkenberg

Hofrichter

et al. 2010

2010 International Conference on High Performance Switching and Routing

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We consider low-complexity, all-optical multi-stage networks with distributed arbitration achieved through minimal per-node buffering. To enhance the saturation throughput of such networks while maintaining low latency at low loads, we examine a novel combination of deterministic (prescheduled) and speculative (eager) packet injections. Prescheduled injections are performed in a time-division-multiplexing (TDM) manner, whereas eager injections follow a packet multiplexing paradigm. Prescheduled injections aim at reducing contention in the fabric, and sustain network throughput when the load is high. Eager injections, on the other hand, ignore the TDM schedule, thus allowing low latency communication when contention is low. In our set of rules that govern the interaction between prescheduled and eager packets, eager packets can be intentionally dropped when they block the progress of prescheduled ones.At the same time a highly efficient end-to-end reliable delivery scheme, implemented at the host adapters, deals with random packet losses in the optical domain, and also recovers the dropped eager packets. Computer simulations demonstrate that our approach can render low-complexity networks, which are amenable to an all-optical implementation, attractive for use in computer interconnects.

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Section: Contribution and Related Workmentioning

confidence: 99%

Towards low-cost high-performance all-optical interconnection networks

Chrysos

Minkenberg

Hofrichter

et al. 2010

2010 International Conference on High Performance Switching and Routing

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“…In the two papers discussed above [14,16], the buffered Banyan switch is constructed of binary switching elements. In [3,32], it was shown that the buffered Banyan switch constructed of switching elements of size greater than two results in a higher throughput.…”

Section: Batcher Banyan Switchesmentioning

confidence: 99%

“…al. [16] showed that, if all the inputs to the switch are of a point-to-point connection type, single-buffered and multiple-buffered Banyan switches result in almost the same throughput. They also showed that, for the mixture of a point-to-point connection and uniform traffic, the multiple-buffered Banyan switch results in throughput improvement of 10% to 15% over the single-buffered Banyan switch, depending on traffic load from a point-to-point connection.…”

Section: Batcher Banyan Switchesmentioning

confidence: 99%

Survey of switching techniques in high‐speed networks and their performance

Oie

Suda

Murata

et al. 1991

Int. J. Satell. Commun.

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One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard‐wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self‐routeing multistage interconnection networks. This is because of the desirable features of multi‐stage interconnection networks such as self‐routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non‐blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non‐blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues.

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Bibliography

2010

Principles of Broadband Switching and Networking

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Performance analysis of buffered banyan networks under nonuniform traffic

Cited by 8 publications

References 11 publications

Towards low-cost high-performance all-optical interconnection networks

Towards low-cost high-performance all-optical interconnection networks

Survey of switching techniques in high‐speed networks and their performance

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