Performance Analysis of a Flexible, Optimized and Fully Configurable FPGA Architecture for Two-Channel Filter Banks

Karloff, Anthony C.; Abdel-Raheem, Esam

doi:10.12785/ijcds/020201

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…When real-time kernels are implemented in software, one of the disadvantages is that the execution time for the service calls will have a minimum and a maximum time [61,62]. The time gap can be big and the worst-case time is one of the factors that will decide the utilization factor of the system.…”

Section: Discussionmentioning

confidence: 99%

Adaptive Fuzzy Hardware Scheduler for Real Time Operating System

Harkut¹

2016

IJCDS

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In embedded system, a real-time operating system (RTOs) is often used to structure the application code and ensure that the deadlines are met by reacting on events in the environment by executing the functions within precise time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical metrics. Generally RTOs are implemented in software, which in turns increases computational overheads, jitter and memory footprint which can be reduced even if not remove completely by utilizing latest FPGA technology, which enables the implementation of a full featured and flexible hardware based RTOs. Scheduling algorithms play an important role in the design of real-time systems. This paper proposes the novel FIS based adaptive hardware task scheduler for multiprocessor systems that minimizes the processor time for scheduling activity which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses feedback which allows processors share of task running on multiprocessor to be controlled dynamically at runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of total task and thus improves efficiency of the entire real-time system. The increased computation overheads resulted from proposed model can be compensated by exploiting the parallelism of the hardware as being migrated to FPGA.

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Section: Discussionmentioning

confidence: 99%

Adaptive Fuzzy Hardware Scheduler for Real Time Operating System

Harkut¹

2016

IJCDS

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Reconfigurable SRTM System for Road Traffic in Kingdom of Bahrain

Elmedany

Al-Omary

Al-Hakim

et al. 2016

Transport and Telecommunication Journal

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This paper presents reconfigurable hardware architecture for smart road traffic system based on Field Programmable Gate Array (FPGA). The design can be reconfigured for different timing of the traffic signals according to the received and collected data read by the different sensors on the road; the design has been described using VHDL (VHSIC Hardware Description Language). The SRTM (Smart Road Traffic Management) System has some more features that help passenger to avoid traffic jamming by sending the collected information through web/mobile applications to find the best road between the start and destination points, which will be displayed on Google maps, at the same time it will also shows the points of traffic jamming on Google maps. SRTM system can also manage emergency vehicles such as ambulance and fire fighter and also can send snapshots and video streaming for different roads and junctions to show the points of traffic jamming. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.

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Performance Analysis of a Flexible, Optimized and Fully Configurable FPGA Architecture for Two-Channel Filter Banks

Cited by 2 publications

References 15 publications

Adaptive Fuzzy Hardware Scheduler for Real Time Operating System

Adaptive Fuzzy Hardware Scheduler for Real Time Operating System

Reconfigurable SRTM System for Road Traffic in Kingdom of Bahrain

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