Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing

Abstract

High-Level Languages (HLLs) for Field-Programmable Gate Arrays (FPGAs) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, programming at a higher level of abstraction is typically accompanied by some loss of performance as well as reduced transparency of application behavior, making it difficult to understand and improve application performance. While runtime tools for performance analysis are often featured in development with traditional HLLs for sequential and parallel programming, HLL-based development for FPGAs has an equal or greater need yet lacks these tools. This article presents a novel and portable framework for runtime performance analysis of HLL applications for FPGAs, including an automated tool for performance analysis of designs created with Impulse C, a commercial HLL for FPGAs. As a case study, this tool is used to successfully locate performance bottlenecks in a molecular dynamics kernel in order to gain speedup.

Communication visualization for bottleneck detection of high-level synthesis applications

“…Related work exists for performance analysis [7] of HDL applications, but that work is not appropritae for HLS applications due to lack of source-code correlation and bandwidth visualizations. Previous work exists for performance analysis of HLS applications and visualization using a modified version of PPW [3]. The techniques in this paper complement this previous timing-based performance analysis by providing instrumentation for bandwidth measurement and communication visualizations.…”

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

“…On the other hand, FPGA performance models have been already proposed in the past ( [10] and especially [11]); however, the HLS tools were not mature enough at that time to be included in the model. A methodology and a model are proposed in [12] and extended in [13], obtaining interesting results using Impulse C. In [14] a mathematical model for pipelined linear algebra applications on FPGAs is presented. Finally, [15] presents the basis of the proposed model.…”

Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems

“…Surprisingly there is little work on more detailed performance analysis for soft-core systems. There are some very notable exceptions ( [4,5]) but do not focus on the specific multi-soft-core and many-soft-core specific issues.…”