Performance analysis: D-Latch modules designed using 18nm FinFET Technology

Vallabhuni, Rajeev Ratna; Yamini, G.; Vinitha, T.; Reddy, Sushanth

doi:10.1109/icosec49089.2020.9215341

Cited by 33 publications

(8 citation statements)

References 15 publications

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“…The presence of multi-gates can better withstand the short channel effects, namely drain-induced barrier lowering, threshold voltage roll off (DV T ) and subthreshold swing SS ( ) [5,6]. Due to these advantages, FinFET is used to design the D-latch module [7].…”

Section: Introductionmentioning

confidence: 99%

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

et al. 2023

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An inversion charge-based threshold voltage model is proposed for 10 nm channel length Tri-gate (TG) FinFET. The variation threshold voltage has been studied with respect to fin width W f i n for different fin height H f i n and channel length L . The effect of width quantization has been explained with the help of the quantum mechanical effect (QME). A precise comparison of threshold voltage in terms of classical mechanics and quantum mechanics depicts the presence of width quantization in short channel device. The improvement of the short channel effects (SCEs), like subthreshold swing (SS), drain-induced barrier lowering (DIBL) and threshold voltage roll off have been studied. The impact of channel length to fin width ratio on DIBL and S S has been examined. The improvement of the SCEs at the same oxide thickness has been observed for high-k dielectric material. The potential and effect of hafnium oxide (HfO2) have been discussed and validated using technology computer-aided design (TCAD) simulation.

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Section: Introductionmentioning

confidence: 99%

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

et al. 2023

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“…These filters provide the linear model, inverse model of the unknown system and predict the present value of the random signal. [16][17][18][19][20][21][22][23][24][25] They can be designed as FIR or IIR filters. The adaptive FIR is more preferred because of its stability and easy updating of the filter coefficients.…”

Section: Introductionmentioning

confidence: 99%

Digital Filter based Adder Module Realization High-Speed Switching Functions

2023

VLSI

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FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to implement any frequency response digitally. Usually, the FIR filters contain multipliers, adders and many delays. As we know, the number of MAC operations (multiply and accumulate) makes the FIR filter less efficient and increases hardware complexity. So in this project, we included DA (Distributed Arithmetic) architecture in designing the efficient adaptive FIR filter. The pipelined Distributive Arithmetic architecture provides less power, less area and high values of throughput in creating an adaptive FIR filter. These are used in Echo cancellations, Radio channel equalizers and speech coding. DA architecture also helps in improving the processing speed of the FIR filter by eliminating the number of multipliers. A reconfigurable filter design can be achieved with the help of this Distributive Arithmetic architecture. Here the sum of the partial products which is pipelined is passed as the input values, and it is stored in the LUT (lookup tables) of the distributive architecture. By replacing the adder of the shift accumulation unit with a carry-save adder, the area of the proposed design is reduced. By placing the ripple carry adder, the size and delay are reduced to a further extent. Here we will use the Xilinx ISE tool to verify the simulation result, area required and time consumed.

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“…In IIR filter, the output depends on past inputs, present inputs and previous outputs. [1][2][3][4][5][6][7][8][9][10][11][12][13][14] The transfer function can be written as…”

Section: Introductionmentioning

confidence: 99%

FPGA based Digital Filter Design for faster operations

2023

VLSI

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The reduced complexity design of the IIR filter is discussed in this paper. The use of the IIR filter has been variably increasing during the present times and they are realtime applications. The filter complexity reduction is done to increase the usage of filters in FPGA. In this method, the coefficients are expressed in the form of 1's and 0's. The multiplied delays have been used which is used to scale down the complexity. Signal Flow Graph plays a critical role in identifying the difficult path. IIR Filter is programmed on basis of the Synchronous Data Flow and Pipelining. The Half Band IIR filters are used for high-performance applications. This design is processed to implement in FPGA which will result in higher speed and the cost will be variably decreased as well as the consumption of power. The entire process is implemented by using the Verilog language which reduces the complication and speeds up the whole process.

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Performance analysis: D-Latch modules designed using 18nm FinFET Technology

Cited by 33 publications

References 15 publications

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

Digital Filter based Adder Module Realization High-Speed Switching Functions

FPGA based Digital Filter Design for faster operations

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