Performance analysis and visualization tools for cell/B.E. multicore environment

Vianney, Duc J.; Haber, Gadi; Heilper, A.; Zalmanovici, Marcel

doi:10.1145/1463768.1463777

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…The above statistics represent the view of program execution from the dynamic timing analysis. It shows that although the CPI of the SPE code dropped from 1.81 to 1.41 after application of compiler optimization flags, the CPI was still high in comparison to most Cell workloads scoring CPIs of 0.7 to 0.9 [9], indicating that further work on improving the performance is required. Another drawback of applying these compiler optimization flags is that the number of dual cycle instructions (issuing two instructions per cycle) decreased in favor of more single cycle instructions.…”

Section: Cell Simulatormentioning

confidence: 99%

Parallelization and Performance Analysis of an IMPES-based Oil-Water Reservoir Simulator

Sibai

Kidwai

2009

2009 11th IEEE International Conference on High Performance Computing and Communications

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Oil reservoir simulation helps in extracting oil and in optimal well placement. This paper presents the parallelization, development, performance analysis, and profiling of a 2-phase oil-water reservoir simulator on a heterogeneous multi-core STI Cell computer. Despite the largely interdependent nature of the oil reservoir model equations, we obtained speedups of 6x with a 1D reservoir data. We boosted the performance by 2x with the right selection of compiler options. We also ran our application on the SystemSim simulator for collection of performance events. Profiling and trace analysis of the application were conducted through VAMPIR, a performance and trace analysis tool for HPC applications. The results from both tools are also presented.

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Section: Cell Simulatormentioning

confidence: 99%

Parallelization and Performance Analysis of an IMPES-based Oil-Water Reservoir Simulator

Sibai

Kidwai

2009

2009 11th IEEE International Conference on High Performance Computing and Communications

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“…Hardware counters can be accessed through the Performance Counter Tool, and runtime traces can be generated using the Performance Debugging Tool. Vianney et al [179] give a step-by-step guide to porting serial applications to the CBEA using these tools, which can be accessed directly, or through the Eclipsebased Visual Performance Analyzer. Further, the IBM Full-System Simulator for the CBEA [144] is a cycle accurate simulator, capable of simulating the PPE and SPE cores, the memory hierarchy, and disk and bus traffic.…”

Section: Cell Bea Languagesmentioning

confidence: 99%

State-of-the-art in Heterogeneous Computing

Brodtkorb

Dyken

Hagen

et al. 2010

Scientific Programming

190

132

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Node level heterogeneous architectures have become attractive during the last decade for several reasons: compared to traditional symmetric CPUs, they offer high peak performance and are energy and/or cost efficient. With the increase of fine-grained parallelism in high-performance computing, as well as the introduction of parallelism in workstations, there is an acute need for a good overview and understanding of these architectures. We give an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine Architecture, graphics processing units (GPUs), and field programmable gate arrays (FPGAs). We present a review of hardware, available software tools, and an overview of state-of-the-art techniques and algorithms. Furthermore, we present a qualitative and quantitative comparison of the architectures, and give our view on the future of heterogeneous computing.

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“…Unfortunately, accelerator engines are notoriously hard to program due to the complexity of their resource management [19,20]. In particular, building an accelerator-based system requires coordinating multiple Instruction Set Architectures (ISAs), which constitute different compilation targets.…”

Section: Commodity Acceleratorsmentioning

confidence: 99%

Reusable software components for accelerator-based clusters

Rafique

Butt

Tilevich

2011

Journal of Systems and Software

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The emerging accelerator-based heterogeneous clusters, comprising specialized processors such as the IBM Cell and GPUs, have exhibited excellent price to performance ratio as well as high energy-efficiency. However, developing and maintaining software for such systems is fraught with challenges, especially for modern high-performance computing (HPC) applications that can benefit the most from leveraging accelerators. If accelerator-based clusters are to deliver on their initial promise to provide a viable and cost-effective HPC solution to researchers and practitioners, one must find a software solution to lower the barrier to entry for the average user. In this paper, we investigate how a software component based approach can be used to provide a reusable and adaptable architecture for executing HPC tasks on accelerator-based clusters. In our implementation, we leverage the lessons from the software engineering research for component-based layered architectures. Our results indicate that the complexity of developing and maintaining accelerator-based cluster software can be as effectively tamed by solid software engineering approaches as that of software in more traditional domains. Specifically, we were able to reuse 83.6% of our implementation code across different architectures and resource configurations, while achieving the overall execution performance only 1.5% off that of an optimally hand-tuned, albeit non-reusable version.

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Performance analysis and visualization tools for cell/B.E. multicore environment

Cited by 5 publications

References 1 publication

Parallelization and Performance Analysis of an IMPES-based Oil-Water Reservoir Simulator

Parallelization and Performance Analysis of an IMPES-based Oil-Water Reservoir Simulator

State-of-the-art in Heterogeneous Computing

Reusable software components for accelerator-based clusters

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