Percolation of Code to Enhance Parallel Dispatching and Execution

Foster, Caxton C.; Riseman, Edward M.

doi:10.1109/t-c.1972.223515

Cited by 46 publications

(11 citation statements)

References 6 publications

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“…Experiments done by Tjaden and Flynn [76] and by Foster and Riseman [216] (and, anecdotally, elsewhere) found that there was only a small amount (about of factor of 2-3) of improvement due to ILP available in real programs. This was dubbed the Flynn bottleneck.…”

Section: Early Experimentsmentioning

confidence: 96%

Instruction-Level Parallel Processing: History, Overview, and Perspective

Rau

Fisher

1993

Instruction-Level Parallelism

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instruction-level parallelism, VLIW processors, superscalar processors, pipelining, multiple operation issue, speculative execution, scheduling, register allocation Instruction-level Parallelism CILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design. Several systems were built, and sold commercially, which pushed ILP far beyond where it had been before, both in terms of the amount of ILP offered and in the central role ILP played in the design of the system. By the end of the decade, advanced microprocessor design at all major CPU manufacturers had incorporated ILP, and new techniques for ILP have become a popular topic at academic conferences. This article provides an overview and historical perspective of the field of ILP and its development over the past three decades.

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Section: Early Experimentsmentioning

confidence: 96%

Instruction-Level Parallel Processing: History, Overview, and Perspective

Rau

Fisher

1993

Instruction-Level Parallelism

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“…Other investigations [5][6][7][8] suggest that the potential for parallelism within basic blocks is limited to an average of no more than two instructions per execution cycle. Parallelism is limited by the data dependencies between instructions and by the short length of basic blocks.…”

Section: The Harp Approachmentioning

confidence: 99%

A parallel pipelined processor with conditional instruction execution

Adams

Steven

1991

SIGARCH Comput. Archit. News

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In a recent paper by Smith, Lam and Horowitz [1] the concept of 'boosting' was introduced, where instructions from one of the possible instruction streams following a conditional branch were scheduled by the compiler for execution in the basic block containing the branch itself. This paper describes how code from both instruction streams following a conditional branch can be considered for execution in the basic block containing the branch. Branch conditions are stored in Boolean registers and all instructions are conditionally executed based on the value in a Boolean register. The two instruction streams can therefore be executed on complementary values of the same Boolean register.

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“…(We will not consider superscalar machines or any other machines that issue instructions out of order. Techniques to reorder instructions at compile time instead of at run time are almost as good [6,7,17], and are dramatically simpler than doing it in hardware. )…”

Section: Class Conflictsmentioning

confidence: 99%

“…Somewhat less parallel loops can be unrolled and then trace-scheduled [5] or software-pipelined [4,111. Even code that is only slightly parallel can be scheduled [6,7,171 to exploit a superscalar or superpipelined machine.…”

Section: Effects Of Optimizing Compilersmentioning

confidence: 99%

Available instruction-level parallelism for superscalar and superpipelined machines

Jouppi

Wall

1989

SIGARCH Comput. Archit. News

117

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Su erscalar machines can issue several instructions perIp cyc e. Superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latency of any functional unit. In this paper these two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism.A parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism for a series of benchmarks. Results of these simulations in the presence of various compiler optimizations are presented.The average degree of superpipelining metric is introduced. Our simulations suggest that this metric is already high for many machines. These machines already exploit all of the instruction-level parallelism available in many nonnumeric applications, even without pa.raIlel instruction issue or higher degrees of pipelining.

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Percolation of Code to Enhance Parallel Dispatching and Execution

Cited by 46 publications

References 6 publications

Instruction-Level Parallel Processing: History, Overview, and Perspective

Instruction-Level Parallel Processing: History, Overview, and Perspective

A parallel pipelined processor with conditional instruction execution

Available instruction-level parallelism for superscalar and superpipelined machines

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