PCB-Interposer-on-DBC Packaging of 650 V, 120 A GaN HEMTs

Lu, Shengchang; Zhao, Tianyu; Burgos, Rolando; Lü, Gongxuan; Bala, Sandeep; Xu, Jianzhong

doi:10.1109/apec39645.2020.9124159

Cited by 8 publications

(7 citation statements)

References 7 publications

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“…In refs. [23,24], 650 V, 120 A respectively 150 A GaN bare dies are sintered onto a DBC substrate. The topside drain, source, and gate pads of the bare dies are contacted by silver-sintered goldplated pins, which are inserted through vias of a very closely mounted PCB.…”

Section: Dbc Substrate/pcb Hybrid Conceptsmentioning

confidence: 99%

Power Module Design for GaN Transistors Enabling High Switching Speed in Multi‐Kilowatt Applications

2023

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The advantages of gallium nitride and silicon carbide transistors over silicon devices are highlighted. The design criteria for power modules in multi‐kilowatt applications to effectively leverage these advantages are described. Various concepts to overcome limitations associated with state‐of‐the‐art power module packaging presented in the literature are summarized and evaluated. A novel power module design comprising a 650 V, 300 A half‐bridge with integrated direct current–link and gate drivers is proposed. The results of a finite‐element analysis of its parasitic elements and subsequent double‐pulse test simulation are presented.

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Section: Dbc Substrate/pcb Hybrid Conceptsmentioning

confidence: 99%

Power Module Design for GaN Transistors Enabling High Switching Speed in Multi‐Kilowatt Applications

2023

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“…, The Shunt-Thru S-parameter measurement setup and its equivalent circuit are presented in Figure 8. After transforming the measured S-parameter matrix into impedance parameters , the impedance can be determined using Equation (8). As previously mentioned, considering is purely resistive and inductive, the desired inductance value is obtained using Equation (7).…”

Section: S-parameter Measurement Techniquesmentioning

confidence: 99%

“…Consequently, it is necessary to minimize the parasitic inductances of commutation loops in order to reduce power losses as well as highfrequency electromagnetic interferences (EMI) [7]. As shown in Figure 1, the commutation Technological improvements have been achieved in recent years to minimize parasitic inductances in GaN transistors packaging, leading to a drastic reduction in the component sizes [8,9]. The monolithic integration of the GaN power transistor and its gate driver, minimizing the gate loop inductance, contributes to modern challenges for highly efficient high-frequency power conversion [10,11].…”

Section: Introductionmentioning

confidence: 99%

“…A calibration procedure and different 2-port measurement techniques are presented in order to obtain the best accuracy in the considered frequency range. The obtained experimental results are then used to validate Technological improvements have been achieved in recent years to minimize parasitic inductances in GaN transistors packaging, leading to a drastic reduction in the component sizes [8,9]. The monolithic integration of the GaN power transistor and its gate driver, minimizing the gate loop inductance, contributes to modern challenges for highly efficient high-frequency power conversion [10,11].…”

Section: Introductionmentioning

confidence: 99%

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Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

et al. 2021

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Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

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“…Application of gallium nitride high-electron mobility transistors (GaN HEMTs) in power converters has the potential to further increase the efficiency and power density because of their low conduction loss, low switching loss, and high temperature capability [1][2][3]. However, packaging these fast-switching devices is challenging because of the requirement for low parasitics and low junction-to-case thermal resistance, ℛ "#$% [4,5]. One of the first steps in developing a device or module package is to layout the package structure and select materials, followed by running electrical and thermal simulations to determine package parasitics and thermal resistances.…”

Section: Introductionmentioning

confidence: 99%

Improved Measurement Accuracy for Junction-to-Case Thermal Resistance of GaN HEMT Packages by Gate-to-Gate Electrical Resistance and Stacking Thermal Interface Materials

Zhang

Buttay

et al. 2022

IEEE Trans. Power Electron.

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Accurate measurements of the junction-to-case thermal resistances of power devices or module packages are necessary for validating the thermal design of the package as well as of the entire converter system. Although accurate measurements can be obtained for Si and SiC packages by the JESD51-14 standard, no standard has been established for GaN packages. A main reason for this shortcoming is the lack of accurate techniques for measuring the device's junction temperature. In this work, a custom package of a (650 V, 150 A) eGaN HEMT with two gate pads was fabricated, and then its junction-to-case thermal resistance was measured by combining two techniques to improve the accuracy: (1) using the device's gate-to-gate electrical resistance as the temperature-sensitive electrical parameter; and (2) measuring the thermal resistance as a function of added layers of thermal interface materials. The first gives a sensitivity of 4.7 mW/ o C and is instantaneous and immune to any transient behavior of the device. The second eliminates the need for accurate measurement of the case temperature. The package's junctionto-case thermal resistance was determined by extrapolating the discrete thermal resistance data points in the plot to zero layer of thermal interface. An analytical expression was derived to guide the extrapolation and was validated by FEA simulations. The measurement procedure was tested using two different thermal interface materials. The difference between the two experimental measurements was within 24%, and both are in good agreement with the simulated result.

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PCB-Interposer-on-DBC Packaging of 650 V, 120 A GaN HEMTs

Cited by 8 publications

References 7 publications

Power Module Design for GaN Transistors Enabling High Switching Speed in Multi‐Kilowatt Applications

Power Module Design for GaN Transistors Enabling High Switching Speed in Multi‐Kilowatt Applications

Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Improved Measurement Accuracy for Junction-to-Case Thermal Resistance of GaN HEMT Packages by Gate-to-Gate Electrical Resistance and Stacking Thermal Interface Materials

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