PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits

Abstract

This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing technology mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing technology mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing technology mapper reduces the balancing overhead by up to 2.7× and with an average of 21% compared to the stateof-the-art academic technology mappers.

Retiming for high-performance superconductive circuits with register energy minimization

“…Thus, many registers are typically inserted between pairs of clocked cells to attain correct logic behaviors. The number of these registers can approach the number of all other cells [12,13]. We elaborate on the register requirement of a FPB circuit using Figure 1(a).…”

“…The circuits built with non-CMOS technologies generally encompass an enormous number of registers or buffer cells due to the physical limitations of fundamental devices [9][10][11]. This unique characteristic motivates researchers to reevaluate the possibility of generalizing or even advancing retiming for evolving non-CMOS applications [12,13].…”

“…To pursue optimal designs, we generalize the retiming transformation to tackle a constrained register energy minimization (CREM) problem, whose objective is to build a wave-pipelined circuit with minimal register energy consumption while meeting performance constraints. Many retiming algorithms have been proposed to address similar problems [1,12,14,[17][18][19][20][21], while none of them are tailored to the CREM problem. An obvious limitation of these algorithms is that they can only be performed after initial registers are inserted either by human effort or by some algorithms.…”

VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology

“…The SFQ circuits used to analyze the VeriSFQ framework are described by the SFQ cells and parameters detailed in [15] and [16]. First, our combinational SFQ circuit designs are structurally modeled at gate-level using the SFQ logic synthesis tool called SFQmap [17], [18]. Then, the structural SFQ circuit models are pre-processed to ensure proper fanout and path balancing before converting the structural model to its hardware description language (HDL) equivalent for UVM-compatibility.…”

“…Given a combinational SFQ circuit, the SFQ logic synthesis tool SFQmap [17], [18] generates its equivalent gate-level structural model. The VeriSFQ framework then extracts the circuit network of gates and wires from this model and analyzes the network to ensure the circuit has primary input fanout of one, SFQ gate fanout of one (adding splitters if needed for fanouts of more than one), and is entirely path balanced as a gate-level pipeline.…”