PBGA warpage and stress prediction for efficient creation of the thermomechanical design space for package-level reliability

Egan, E.; Kelly, Christopher V.; Herard, L.

doi:10.1109/ectc.1999.776384

Cited by 23 publications

(6 citation statements)

References 12 publications

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“…Initial modeling has been performed based on the conventional packaging methodology [5,6,7], thermal loading due to CTE mismatch between different packaging materials during dieattach, wirebond and encapsualtion processes. Deformation of the thin cap on microrelay die due to packaging process was the main aim of the modeling and how it can be minimized by selecting the right material and change in the process methodology.…”

Section: Dieattachmentioning

confidence: 99%

“…Product realization of a MEMS product depends more on the successful packaging and reliability. Cantilever FEA modeling has been widely used in conventional packaging to reduce the cycle time for product development by structural and mechanical modeling [5,6]. The same principles may be used for MEMS packaging also to optimize the package design.…”

Section: Introductionmentioning

confidence: 99%

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<title>Packaging issues using FEA and experimental verification on a Si-based capacitive microrelay</title>

Premachandran¹,

Zhang²,

Chai³

et al. 2001

SPIE Proceedings

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A Si based capacitive microrelay has been packaged in a premolded package and the packaging issues has been studied and verified by FEA and experimental methods. A quasi-3D finite element modeling has been used to understand the thin cap warpage on the microrelay under different process conditions. Experimental verification on the cap warpage showed that thermal loading is not the only contributing parameter for the cap warpage. A modified model with air loading effect and thermal loading effect validated the experimental result. Solution to overcome this problem has been studied with a hole in the package and reinforcement of cap with epoxy.

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Section: Dieattachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

<title>Packaging issues using FEA and experimental verification on a Si-based capacitive microrelay</title>

Premachandran¹,

Zhang²,

Chai³

et al. 2001

SPIE Proceedings

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“…Chips can undergo stress due to signal density, voltage, temperature, humidity, and current 9,10 . However, there has been relatively little work in the area of signal density stress level prediction.…”

Section: Introductionmentioning

confidence: 99%

On-board SRAM signal density stress prediction

Hsieh

Sharma

2006

SPIE Proceedings

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Static Random Access Memory (SRAM) chips undergo several types of stress in the field. Existing work has concentrated primarily on humidity and thermal stress; there has been relatively little emphasis on signal density stress prediction. Objectives of this study were to (1) explore the impact of signal density stress on SRAM functionality, (2) observe thermal profile differences under signal density stress over time, (3) predict stress levels using artificial neural network models, and (4) develop a generic methodology for signal density stress prediction. An 8051 programming board containing an SRAM chip was used. Two kinds of signal density stress were investigated-varying the content written to memory, and varying signal frequency in accessing SRAM through flash memory. Preliminary experiments suggest that both types of stress impact the SRAM thermal profile. Thermal profile data were used to build back propagation neural network models; 70% of the data was used to build the models and 30% was used for testing. Various neural network training functions and topologies were used to predict chip stress level given thermal profile data. Data from both the die area and the entire chip were used. For both types of stress, using data from the die area in a network with a 3-3-1 topology yielded the lowest average error rate-1.3% for data content stress level prediction and 7.6 % for signal frequency stress level prediction. The trainRP function resulted in a lower error rate than other training functions that were evaluated.

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“…However, product weaknesses such as physical and logic faults, which are often caused by signal frequency stress, are not detectable during the manufacturing process and can result in failures in the field. Typical accelerated stress categories include temperature, mechanical shock and vibration, power surge, voltage variation and electromagnetic interference [11,12]. However, there has been relatively little emphasis on microcontroller frequency stress level prediction.…”

Section: Introductionmentioning

confidence: 99%