Payload and Scientific Investigation Objectives of the Flying Laptop

Walz, Steve; Lengowski, Michael; Schoenermark, Maria von

doi:10.1515/9783110919806.153

Cited by 2 publications

(1 citation statement)

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“…8,9) The satellite utilizes three high resolution camera systems with ground sampling distance of 25/100/200 m, respectively, a high accurate attitude control system with pointing knowledge of better than 7 arcseconds and a 0.5 Gbps Ka-band communication system, all of which are exceptional for small satellites. The satellite system configuration is illustrated in Fig.…”

Section: Flying Laptop Satellitementioning

confidence: 99%

Development of a Hardware-in-the-Loop Simulation Environment on a MDVE for FPGA-based On-board Computing Systems

Kuwahara

Falke

Ziemke

et al. 2009

Trans. JSASS Space Tech. Japan

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The goal of this paper is to describe the development of a hardware-in-the-loop simulation and verification environment for Field Programmable Gate Array (FPGA) based on-board computing systems. The underlying simulation environment is the Model-based Development and Verification Environment (MDVE). MDVE is an infrastructure for model-based engineering developed by EADS Astrium. A simulation environment based on MDVE was developed at the Universität Stuttgart. Recently, the demand on applying new high density FPGA technologies for innovative spacecraft on-board computing systems is rising. The small satellite "Flying Laptop" which is built by the Universität Stuttgart is the demonstrator of a FPGA-based on-board computer. In order to develop and verify the hardware and control algorithm of the computer, an extended simulation interface between MDVE and FPGA-based computing systems is established. This environment is capable of software verification and real-time simulation/verification configuration, and enables not only on-board software development but also functional real-time hardware evaluation of all the satellite components under precise space environment models. This paper describes the detailed implementation of this simulation interface and illustrates the obtained simulation results on attitude control algorithm verification and power budget calculation as well as communication timing analysis, which ensure the validity of the implementation.

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Section: Flying Laptop Satellitementioning

confidence: 99%

Development of a Hardware-in-the-Loop Simulation Environment on a MDVE for FPGA-based On-board Computing Systems

Kuwahara

Falke

Ziemke

et al. 2009

Trans. JSASS Space Tech. Japan

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FPGA On-Board Computer design based on hierarchical fault tolerance

Xing

Sun

2008

2008 2nd International Symposium on Systems and Control in Aerospace and Astronautics

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Safety is a crucial requirement of On-Doard Computer (ODC) design of a satellite, especially for the new type ODC-takes FPGA as central processor. Upon that this paper proposes a plan of FPGA ODC design and adds hierarchical fault tolerant concept to enhance the reliability of the ODC system. The fault tolerant architecture can be divided into three hierarchic ranks, containing single-CPU reconfiguration, component unit transfer and dual-CPU subrogation. One of the above fault manage mode will be chosen to deal with problems according to error situation in-orbit. In the worst cases, all three modes may be used. The last part of the paper gives the functional verification approach under development for the hierarchical fault tolerant ODC design.I.

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Payload and Scientific Investigation Objectives of the Flying Laptop

Cited by 2 publications

References 0 publications

Development of a Hardware-in-the-Loop Simulation Environment on a MDVE for FPGA-based On-board Computing Systems

Development of a Hardware-in-the-Loop Simulation Environment on a MDVE for FPGA-based On-board Computing Systems

FPGA On-Board Computer design based on hierarchical fault tolerance

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