Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

Rigo, Alvise; Pinto, Christian; Pouget, Kevin; Raho, Daniel; Dutoit, Denis; Martinez, P.-Y.; Doran, Chris; Benini, Luca; Mavroidis, Iakovos; Marazakis, Manolis; Bartsch, V.; Lonsdale, Guy; Pop, Antoniu; Goodacre, John; Colliot, Annaik; Carpenter, Paul; Radojković, Petar; Pleiter, D.; Drouin, Dominique; Dinechin, Benoît Dupont de

doi:10.1109/dsd.2017.37

Cited by 24 publications

(18 citation statements)

References 11 publications

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“…ExaNoDe [16] focuses on the design of a highly energy efficient and highly integrated heterogeneous compute node targeting exascale level computing. The design of the target node mixes low-power processors, heterogeneous co-processors and includes advanced hardware integration technologies with a novel memory system.…”

Section: Related Workmentioning

confidence: 99%

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Ciobanu

Stramondo

Vărbănescu

et al. 2018

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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Reconfigurable hardware is becoming increasingly mainstream, evolving to a valid alternative to Graphics Processing Units-based hardware accelerators. However, several major challenges remain for migrating existing software to heterogeneous reconfigurable architectures. The EXTRA project aims to develop an integrated environment for developing and programming reconfigurable architectures. The EXTRA platform enables the joint optimization of architecture, tools, and reconfiguration technology, and targets the future High Performance Computing hardware nodes. In this paper, we present four innovative EXTRA technologies: (1) a hardwaresoftware co-design framework; (2) a parallel memory system; (3) a decoupled access execute framework for reconfigurable technology; and (4) transparent access and virtualization of reconfigurable hardware accelerators. Moreover, we describe how the EXTRA technologies targeting the Amazon F1 cloud compute instances can be used in medical applications such as the retinal image segmentation. CCS CONCEPTS • Computer systems organization → Reconfigurable computing; Data flow architectures; • Hardware → Hardware accelerators; Hardware-software codesign;

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Section: Related Workmentioning

confidence: 99%

Extra

Ciobanu

Stramondo

Vărbănescu

et al. 2018

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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“…By appropriately configuring the cache policy each remote memory access can be cached locally. This work was continued in the ExaNoDe [34] and EuroEXA [31] projects. The dReDBox project [4] also proposes a customizable low-power architecture comprised of hot-pluggable modules that provide compute, memory and accelerators resources.…”

Section: Introductionmentioning

confidence: 99%

“…In the disaggregated design, individual components such as processor, memory and storage are interconnected over a network [14,21,28,36,40] rather than being restricted to a bus on a single board [33]. The EuroEXA family of projects [14,34], for instance, provides a global physical address space in which cores can access remote memory via RDMA and direct load-store instructions. In comparison with traditional shared memory processors, the focus is on sharing of memory capacity, rather than coherent sharing of data.…”

mentioning

confidence: 99%

Contention-aware application performance prediction for disaggregated memory systems

Zacarias

Nishtala

Carpenter

2020

Proceedings of the 17th ACM International Conference on Computing Frontiers

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Disaggregated memory has recently been proposed as a way to allow flexible and fine-grained allocation of memory capacity to compute jobs. This paper makes an important step towards effective resource allocation on disaggregated memory systems. Specifically, we propose a generic approach to predict the performance degradation due to sharing of disaggregated memory. In contrast to prior work, cache capacity is not shared among multiple applications, which removes a major contributor to application performance. For this reason, our analysis is driven by the demand for memory bandwidth, which has been shown to have an important effect on application performance. We show that profiling the application slowdown often involves significant experimental error and noise, and to this end, we improve the accuracy by linear smoothing of the sensitivity curves. We also show that contention is sensitive to the ratio between read and write memory accesses, and we address this sensitivity by building a family of sensitivity curves according to the read/write ratios. Our results show that the methodology predicts the slowdown in application performance subject to memory contention with an average error of 1.19% and max error of 14.6%. Compared with stateof-the-art, the relative improvements are almost 24% on average and 33% for the worst case. CCS CONCEPTS • Computing methodologies → Modeling methodologies.

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“…These advancements have become even more prominent as we rapidly approach the dawn of exascale computing, with machines capable of performing a million trillion floating-point calculations per second. [1][2][3] However, to enable these massive calculations, recent exascale computing guidelines [4][5][6] have strongly cautioned that this increase in computing power should only require a modest increase in power consumption (to offset both operation costs and deleterious climate change effects).…”

Section: Introductionmentioning

confidence: 99%

Field Programmable Gate Arrays (FPGAs) for Enhancing the Speed and Energy Efficiency of Quantum Dynamics Simulations

Rodriguez-Borbon¹,

Kalantar²,

Yamijala³

et al. 2020

Preprint

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We present the first application of field programmable gate arrays (FPGAs) as new, <i>customizable</i> hardware architectures that can be harnessed for the fast and energy-efficient calculation of quantum dynamics simulations of large chemical/material systems. Instead of tailoring the software to fixed hardware (which is the typical case for writing quantum chemistry code for CPUs/GPUs), FPGAs allow us to <i>directly customize the underlying hardware</i> - even at the level of specific electrical signals in the circuit - to give a truly optimized computational performance for complex quantum dynamics calculations. By offloading the most intensive and repetitive calculations onto an FPGA, we show that the computational performance of our hardware implementation for real-time electron dynamics calculations can even exceed that of optimized commercial mathematical libraries running on high-performance GPUs. In addition to this impressive computational speedup, we show that FPGAs are immensely energy-efficient and consume 4 times less energy than modern GPU or CPU architectures. These energy savings are a practical and important metric for supercomputing centers (several of which exceed over $1 million in power costs alone), as exascale computing capabilities become more widespread and commonplace. Taken together, the implementation techniques and performance metrics of our study demonstrate that FPGAs could play a promising role in upcoming quantum chemistry and materials science applications, particularly for the acceleration and energy-efficient execution of quantum dynamics calculations.

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Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

Cited by 24 publications

References 11 publications

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Contention-aware application performance prediction for disaggregated memory systems

Field Programmable Gate Arrays (FPGAs) for Enhancing the Speed and Energy Efficiency of Quantum Dynamics Simulations

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