PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures

Christen, Matthias; Schenk, Olaf; Burkhart, Helmar

doi:10.1109/ipdps.2011.70

Cited by 271 publications

(201 citation statements)

References 19 publications

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“…Most domain-specific languages [13,5,25] for stencil computations target both multicores and GPUs. Of these, [13,5] do not support shared memory or temporal tiling or large ghost zones on GPUs.…”

Section: Compiler Optimizations Dsls and Programming Models For Stenmentioning

confidence: 99%

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Compiler-based code generation and autotuning for geometric multigrid on GPU-accelerated supercomputers

et al. 2017

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GPUs, with their high bandwidths and computational capabilities are an increasingly popular target for scientific computing. Unfortunately, to date, harnessing the power of the GPU has required use of a GPU-specific programming model like CUDA, OpenCL, or OpenACC. As such, in order to deliver portability across CPU-based and GPU-accelerated supercomputers, programmers are forced to write and maintain two versions of their applications or frameworks. In this paper, we explore the use of a compiler-based autotuning framework based on CUDA-CHiLL to deliver not only portability, but also performance portability across CPU-and GPU-accelerated platforms for the geometric multigrid linear solvers found in many scientific applications. We show that with autotuning we can attain near Roofline (a performance bound for a computation and target architecture) performance across the key operations in the miniGMG benchmark for both CPU-and GPU-based architectures as well as for a multiple stencil discretizations and smoothers. We show that our technology is readily interoperable with MPI resulting in performance at scale equal to that obtained via hand-optimized MPI+CUDA implementation.

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Section: Compiler Optimizations Dsls and Programming Models For Stenmentioning

confidence: 99%

“…Of these, [13,5] do not support shared memory or temporal tiling or large ghost zones on GPUs. Halide [25], as discussed earlier, is a mature DSL which is designed primarily for image processing pipeline.…”

Section: Compiler Optimizations Dsls and Programming Models For Stenmentioning

confidence: 99%

Compiler-based code generation and autotuning for geometric multigrid on GPU-accelerated supercomputers

et al. 2017

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“…Another body of work around stencil computations have developed domain specific languages and compilers specialized for stencils [17]- [19]. These work also employ variations of tiling combined with additional optimizations.…”

Section: Related Workmentioning

confidence: 99%

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

Deest

Yuki²,

Rajopadhye³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. The optimal choice depends on problem sizes and performance goals. I. INTRODUCTIONIterative stencil computations arise in many application domains, ranging from medical imaging to numerical simulation. Since they are computationally demanding, a large body of work addressed the problem of parallelizing and optimizing stencils for multi-cores, GPUs, and FPGAs.Earlier attempts targeting FPGAs showed that the performance of such accelerators is a complex interplay between the raw FPGA computing power, the amount of on-chip memory, and the performance of the external memory system [1]- [8]. They also illustrate different application requirements. For example, in the context of embedded vision, designers often seek the cheapest design achieving real-time performance constraints (e.g., 4K@60fps). In an exascale context, they may want to maximize performance (measured in ops-persecond) for a given FPGA board, while maintaining power dissipation to a minimum. Therefore, we explore a family of design options that can accommodate a large set of constraints, by exposing trade-offs between computing power, bandwidth requirements, and FPGA resource usage. We focus on system-level issues. Our aim is not to provide hand-optimized FPGA implementations. We have developed a code generator that produces HLS-optimized C/C++ descriptions of accelerator instances, leaving low-level decisions to the HLS back-end.Our designs build upon the tiling transformation, that we use to balance on-chip memory cost and off-chip bandwidth. The design space we explore can be characterized by the following design knobs.

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“…Alone for the domain of stencil computations, there are, e.g., Liszt [13] (or the newer DeLite), Pochoir [39], and PATUS [11]. Each one of these is pursuing specific goals: Liszt adds abstractions to Java to make stencils programming easier, also for unstructured problems; Pochoir employs a divide-andconquer skeleton on top of the parallel C extension Cilk to make stencil computations cache-oblivious; PATUS achieves performance by auto-tuning.…”

Section: Domain-specific Source Languagesmentioning

confidence: 99%

ExaStencils: Advanced Stencil-Code Engineering

Lengauer

Apel

Bolten

et al. 2014

Lecture Notes in Computer Science

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Abstract. Project ExaStencils pursues a radically new approach to stencil-code engineering. Present-day stencil codes are implemented in general-purpose programming languages, such as Fortran, C, or Java, or derivates thereof, and harnesses for parallelism, such as OpenMP, OpenCL or MPI. ExaStencils favors a much more domain-specific approach with languages at several layers of abstraction, the most abstract being the mathematical formulation, the most concrete the optimized target code. At every layer, the corresponding language expresses not only computational directives but also domain knowledge of the problem and platform to be leveraged for optimization. This approach will enable a highly automated code generation at all layers and has been demonstrated successfully before in the U.S. projects FFTW and SPIRAL for certain linear transforms. The Challenges of Exascale ComputingThe performance of supercomputers is on the way from petascale to exascale. Software technology for high-performance computing has been struggling to keep up with the advances in computing power, from terascale in 1996 to petascale in 2009 on to exascale, now being only a factor of 30 away and predicted for the end of the present decade. So far, traditional host languages, such as Fortran and C, being equipped with harnesses for parallelism, such as MPI and OpenMP, have taken most of the burden, and they are being developed further with some new abstractions, notably the partitioned global address space (PGAS) memory model [1] [10]. Yet, the sequential host languages remain generalpurpose: Fortran or C or, if object orientation is desired, C ++ or Java.The step from petascale to exascale performance challenges present-day software technology much more than the advances from gigascale to terascale and terascale to petascale have. The reason is the explicit treatment of the massive parallelism inside one node of a high-performance cluster cannot be avoided any longer. That is, the cluster nodes must be manycores with high numbers of cores. The reorientation of the computer market from single cores to multicores and manycores has been observed with concern [29]. In the high-performance market, the situation is somewhat alleviated by the fact that the additional cycles that large numbers of cores provide are actually being yearned for. But, the question of how to exploit them with efficient and robust software remains.While the potential for massive parallelism on and off the chip is the single most serious challenge to exascale software technology, other challenges take on a high priority and are frequently being mentioned, such as power conservation, fault tolerance and heterogeneity of the execution platform [2]. At best, one would strive for performance portability, i.e., the ability to switch the software with ease from one platform, when it is being decommissioned, to the next, while maintaining highest performance. ExaStencils Application Domain: Stencil CodesStencil codes have extremely high significance and value for a good-sized c...

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PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures

Cited by 271 publications

References 19 publications

Compiler-based code generation and autotuning for geometric multigrid on GPU-accelerated supercomputers

Compiler-based code generation and autotuning for geometric multigrid on GPU-accelerated supercomputers

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

ExaStencils: Advanced Stencil-Code Engineering

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