Patterning strategies in nanofabrication : from periodic patterns to functional nanostructures

Abstract

Chapter 2 -Unconventional strategies in nanofabrication:patterning principles The drive towards the miniaturization of electronic circuits comes at the penalty of higher resistances and higher levels of power dissipation. The advantages of using light instead of electrons as the information carrier account for the efforts that are undertaken to progress the high-density integration and system performance towards all-optical circuits by the incorporation of photonic crystal (PhC) structures. [7] PhC structures represent a novel class of optical materials (also present in nature [8] ) that contain periodic modulations in dielectric contrast resulting from two- [9] and/or threedimensional [10] structuring of matter at the scale of the optical wavelength. The resulting characteristic photonic band gap (PBG) for a specific range of frequencies [11] is responsible for the corresponding strong confinement and localization of light, [12] and Chapter 6 describes the entire engineering technology to set the design rules for optimal LOCOS inversion in terms of layer thickness and etch selectivities. The partial conversion of silicon nitride (Si 3 N 4 ) to silicon oxynitride (SiN x O y ) during the oxidation step of the LOCOS procedure is shown by etch rate measurements. The use of guidelines is shown to systematically locate the optimal parameters for silicon etching at high anisotropy and high etch selectivity using ultrathin SiO 2 etch masks.Chapter 7 presents the successful fabrication and replication of 2D PhCWGs on silicon-on-insulator (SOI) substrates by elaborating on the technological advancements in NIL processing set in Chapter 6. Local examination using photon scanning tunneling microscopy (PSTM) has been carried out to assess the guiding properties of the resulting 2D PhCWGs (in terms of confinement and loss of the propagating light) at wavelengths in the telecommunication range. References Introduction1965 is the year that the co-founder of Intel ® Gordon Moore came with his prediction, now known as Moore's Law, that the number of transistors on a chip doubles every two years. architecture. With about twice the density of the preceding 65 nm technology, this technology packs about double the number of transistors into the same silicon space (to about one billion for a quad-core processor).[2]The International Technology Roadmap for Semiconductors (ITRS) [3] is an assessment of the Semiconductor Industry Association (SIA) [4] to chart the necessary advancements in technology by identifying the technological challenges for the continuation of Moore's Law (Fig. 2.2). [3]8Unconventional strategies in nanofabrication:patterning principlesThe main challenge is to meet the stringent industrial requirements of cost-effective manufacturing with excellent critical dimension (CD) control in combination with accurate control of positioning (overlay) at ever-increasing resolution. [5] As shown in The inherent limitations of photolithography (in general) with respect to resolution (R) and depth-of-focus (D...