Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

Abstract

International audienc

Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth

“…As shown in a previous paper, 18 nitride spacer etching in CH 3 F/O 2 /He plasmas leads to the formation of an oxidized SiO x F y layer on top of the silicon substrate when the plasma lands on the silicon surface. We also demonstrated by AR-XPS that a carbon peak, at the binding energy of 283.8 eV corresponding to C-Si bonds 20,21 is located at the SiO x F y /Si interface.…”

“…It has been shown in a previous paper that the silicon consumption generated in source/drain regions by the CH 3 F/O 2 /He nitride spacer etch process is mainly caused by creation of a reactive SiO x F y layer on top of the silicon surface, 18 which is later removed by the wet HF clean used before silicon epitaxy. II) left on the silicon surfaces by the nitride spacer etch step.…”

Role of Trimethylaluminum in Low Temperature Atomic Layer Deposition of Silicon Nitride

“…Thin silicon nitride (Si 3 N 4 ) films are widely used for gate spacers and diffusion barriers in the microelectronics industry. − Typically, Si 3 N 4 films are grown by low-pressure chemical vapor deposition (LPCVD) at high temperatures (750 °C) or by plasma-enhanced chemical vapor deposition (PECVD) at lower temperatures. − However, as devices continue to scale down, the requirements for conformality and step-coverage are becoming more stringent, making CVD-based processes inadequate . In contrast, atomic layer deposition (ALD) is a technique based on self-limiting surface reactions, which allows for the growth of high quality, highly conformal thin films on both planar and 3-D (e.g., trenches, nanorods, nanoparticles, etc.)…”

Two-step cycling process alternating implantation and remote plasma etching for topographically selective etching: Application to Si3N4 spacer etching

“…8 Indeed, the ion-neutral synergy that drives the etching mechanism in CW plasma induces the creation of a few-nanometer-thick reactive layers (ion energies >15-20 eV), which compromise the etch precision. 9 Blanc et al showed that improved spacer process performance can be obtained by using synchronous pulsed plasma technology. 10 The switching on and off in a synchronous manner of both the source and bias powers at a low duty cycle allows us to decrease the average ion energy and the plasma chemical reactivity (more molecular than atomic), which ultimately reduce plasma induced damage.…”