2001
DOI: 10.1117/12.435745
|View full text |Cite
|
Sign up to set email alerts
|

Patterning 80-nm gates using 248-nm lithography: an approach for 0.13-μm VLSI manufacturing

Abstract: We have developed an 80nm poly gate patterning process for 0.13µm VLSI manufacturing using 248nm lithography with double-exposure phase-shifting technique. We show that: Systematic intra-field line width variation can be controlled within 6nm (3σ), and total wafer variation across the wafer held to within 10nm (3σ), with good line-end shortening control for gate endcaps. The k1 factor is < 0.2 (80nm target gate length in 320nm pitch).

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Year Published

2001
2001
2003
2003

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
references
References 6 publications
0
0
0
Order By: Relevance