Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems

Brunner, Timothy A.; Zhou, Yue; Wong, Cheuk Wun; Morgenfeld, Bradley; Leino, Gerald; Mahajan, S.

doi:10.1117/12.2218630

Cited by 11 publications

(11 citation statements)

References 4 publications

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“…The surface height maps are determined from the interferometer related to the phase of the reflected λ=635nm wave from the wafer. If the substrate is coated with transparent thin films, then "false topography" can be significant because portions of the reflected wave come from below the top surface 10 .…”

Section: Fizeau Interferometrymentioning

confidence: 99%

New wave front phase sensor used for 3D shape measurements of patterned silicon wafers

Trujillo-Sevilla

Gómez-Cárdenes

Roqué-Velasco

et al. 2022

International Conference on Extreme Ultraviolet Lithography 2022

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On product overlay (OPO) is one of the most critical parameters for the continued scaling according to Moore's law. Without good overlay between the mask and the silicon wafer inside the lithography tool, yield will suffer 1 . As the OPO budget shrinks, non-lithography process induced stress causing in plane distortions (IPD) becomes a more dominant contributor to the shrinking overlay budget 2 . To estimate the process induced in-plane wafer distortion after cucking the wafer onto the scanner board, a high-resolution measurement of the freeform wafer shape of the unclamped wafer with the gravity effect removed is needed. Measuring both intra and inter die wafer distortions, a feed-forward prediction algorithm, as has been published by ASML, minimizes the need for alignment marks on the die and wafer and can be performed at any lithography layer 3 . Up until now, the semiconductor industry has been using Coherent Gradient Sensing (CGS) interferometry or Fizeau interferometry to generate the wave front phase from the reflecting wafer surface to measure the free form wafer shape 3,4 . In this paper, we present a new method to generate a very high-resolution wave front phase map of the reflected light from a patterned silicon wafer surface that can be used to generate the free form wafer shape. We show data using a WFPI patterned wafer geometry tool to acquire 3.4 million data points on a 200mm patterned silicon wafer with 96µm spatial resolution with a data acquisition time of 5 seconds.

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Section: Fizeau Interferometrymentioning

confidence: 99%

New wave front phase sensor used for 3D shape measurements of patterned silicon wafers

Trujillo-Sevilla

Gómez-Cárdenes

Roqué-Velasco

et al. 2022

International Conference on Extreme Ultraviolet Lithography 2022

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“…Gao et al 92 investigated warping of silicon wafers in ultra-precision grinding-based back-thinning process and then established a mathematical model to describe wafer warping during the thinning process using the elasticity theory. Brunner et al 29 provided an overview of the patterned wafer geometry (PWG) methodology to improve lithographic patterning quality by investigating process-induced focus issues and overlay problems. Hsieh et al 93 presented an innovative full-field wafer warpage measurement technique for detecting wafer warpage and surface topology during the MOCVD epitaxial process.…”

Section: Semiconductor Wafer Warpage Analysismentioning

confidence: 99%

“…As the thickness of the wafer decreases and large stresses are induced during manufacturing processes such as film deposition, CMP, lithography, etch, and various thermal processes, an increasing trend of wafer warpage has been seen 27,28 . In the past few years, several patterned wafer geometry (PWG) metrology tools have been employed to measure wafer distortion 29,30 . Thus, in this research, we consider semiconductor wafer defect bin data combined with wafer warpage information and propose a novel hybrid resampling technique to improve the performance of wafer defect bin classifiers.…”

Section: Introductionmentioning

confidence: 99%

“…27,28 In the past few years, several patterned wafer geometry (PWG) metrology tools have been employed to measure wafer distortion. 29,30 Thus, in this research, we consider semiconductor wafer defect bin data combined with wafer warpage information and propose a novel hybrid resampling technique to improve the performance of wafer defect bin classifiers. The rest of this article is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

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A novel hybrid resampling for semiconductor wafer defect bin classification

Park

Pan

Montgomery

2022

Quality & Reliability Eng

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Generally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non-defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.

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“…Optical profilometry based on interferometry was shown to be able to measure in-process patterned wafers and investigate process-induced focus and overlay problems [4]. While this technique is very useful for a global view at the wafer scale, there is a need for a more accurate view at the die scale.…”

Section: Introductionmentioning

confidence: 99%

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

Balan

Michel

Mendes

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nanotopography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.

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Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems

Cited by 11 publications

References 4 publications

New wave front phase sensor used for 3D shape measurements of patterned silicon wafers

New wave front phase sensor used for 3D shape measurements of patterned silicon wafers

A novel hybrid resampling for semiconductor wafer defect bin classification

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

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