Patterned electrode vertical field effect transistor: Theory and experiment

Abstract

We present a theoretical and experimental investigation of the recently reported new architecture of a patterned electrode vertical field effect transistor (PE-VFET). The investigation focuses on the role of the embedded source electrode architecture in the device behavior. Current-voltage characteristics was unraveled through the use of a self-consistent numerical simulation resulting in guidelines for the PE-VFET architecture regarding the On/Off current ratio, output current density, and apparent threshold voltage. Current modulation characteristics are obtained through the formation of virtual contacts at the PE nano-features (i.e., perforations) under gate bias, which lead to the formation of vertical channels under drain bias. As the vertical channel is formed the device characteristics change from contact-limited to space-charge-limited. The analytical model strength is shown with the parameter extraction procedure applied to a measured PE-VFET device fabricated using block copolymer lithography and with the appropriate simulation results.

Copper phthalocyanine based vertical organic field effect transistor with naturally patterned tin intermediate grid electrode

“…Ben-Sasson and Tessler [40] proposed a model that describes the electrical behaviour of VOFETs in which the current modulation characteristics are obtained through the formation of virtual contacts at the intermediate electrode pinholes under gate bias, which lead to the formation of vertical channels under drain bias. These authors use patterned electrodes with controlled perforations whereas in our case, the pinholes naturally occur in the intermediate electrode, but the conclusions apply equally.…”

Patterned electrode vertical OFET: analytical description, switching mechanisms, and optimization rules

“…The transparency is obtained with the use of perforated architecture (i.e. Patterned Electrode (PE)) accessible through various methods: Ultra-thin metallic layer evaporation over high roughness surface [2] or over polymeric surfaces [4] , carbon nanotube dilute solution deposition [1,6,7] , soft-lithography methods such as the one based on self-assembled Block Copolymers [8,9] which are amenable for large area fabrication but could also determine features shape and size in the scale of tens of nm.…”

“…Numerical analysis and measurements of devices with varying PE thickness support the dual role of the gate electrode. The analytical description, relevant only in extreme gate biasing conditions and for ideal Schottky barrier devices, does not consider the role of most of the PE structural parameters, the understanding of which is essential to optimize device performances and in Part IV they are reviewed briefly according to the work presented at ref [9] . Part V summarizes our results and future research directions.…”

“…In Part I we provide a description of the device architecture and its electrical behavior based on a self-consistent numerical analysis provided in ref [9] . This description will allow us to detail the basic characteristics of the device.…”

Fast switching characteristics in vertical organic field effect transistors

“…14,16 It was shown that the device ON/OFF ratio depends on the aspect ratio of the holes or perforations in the source. One way to change this aspect ratio is to keep the size of the holes constant (85 nm) and vary the thickness of the source electrode.…”