Pattern Training, Inference, and Regeneration Demonstration Using On‐Chip Trainable Neuromorphic Chips for Spiking Restricted Boltzmann Machine

Shin, U.; Ishii, Masatoshi; Okazaki, Atsuya; Ito, Megumi; Rasch, Malte J.; Kim, Wanki; Nomura, Akiyo; Choi, Wonseok; Koh, Dooyong; Hosokawa, Kohji; BrightSky, M.; Munetoh, Seiji; Kim, Sang-Bum

doi:10.1002/aisy.202200034

Cited by 4 publications

(4 citation statements)

References 37 publications

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“…supported the detailed experiment result of the previous study [ 221 ] and successfully performed the MNIST test and image reconstruction based on on‐chip training. [ 264 ]…”

Section: System‐level Realizationmentioning

confidence: 99%

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Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Byun

Choi

Kwon

et al. 2022

Adv Materials Technologies

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Nonvolatile memory (NVM)‐based neuromorphic computing has been attracting considerable attention from academia and the industry. Although it is not completely successful yet, remarkable achievements have been reported pertaining to synaptic devices that can leverage NVM capable of storing multiple states. The analog synaptic devices performing computation similar to biological nerve systems are crucial in energy‐efficient analog neuromorphic computing systems. To use NVM as an analog synaptic device, researchers focus on improving device characteristics. Among various characteristics, the most challenging one is linearity and symmetry of synaptic weight update that is required for on‐chip training. In this regard, this review paper discusses recent synaptic device improvements focusing on novel schemes tailored for each NVM device to improve the linearity and symmetry. In addition to device‐level studies, recent research achievements are reviewed expanded up to chip‐level studies because in realizing neuromorphic hardware systems beyond a single synaptic device, several considerations and requirements are needed to confirm for high‐level design, and accordingly, cooptimize among synaptic devices, synapse arrays, electrical circuits, neural networks, algorithms, and implementation. Also, this review paper introduces various circuit and algorithmic approaches to compensate for the non‐ideality of the analog synaptic device.

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“…supported the detailed experiment result of the previous study [ 221 ] and successfully performed the MNIST test and image reconstruction based on on‐chip training. [ 264 ]…”

Section: System‐level Realizationmentioning

confidence: 99%

“…Shin et al supported the detailed experiment result of the previous study [221] and successfully performed the MNIST test and image reconstruction based on on-chip training. [264] Figure 15. a) Two passive synapse arrays and OPAMP neurons are integrated on PCB separately.…”

Section: Fully Hardware-integrated On-chipmentioning

confidence: 99%

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Byun

Choi

Kwon

et al. 2022

Adv Materials Technologies

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“…Thus, the SNN can imitate timedependent biological neural reactions, such as leaky integrateand-fire (LIF) or local learning rules including STDP. 40 Additionally, due to the SNN information being delivered by spikes and generating the output whenever it overcomes the internal threshold value, the SNN exhibits a sparse network state, which has the advantage of low-power consumption in hardware implementation. 41 The RBM is a neural network that simplifies the learning computation of Boltzmann machines.…”

mentioning

confidence: 99%

“…An SNN closely mimics a biological neural network, and unlike a deep neural network (DNN), it contains temporal information. Thus, the SNN can imitate time-dependent biological neural reactions, such as leaky integrate-and-fire (LIF) or local learning rules including STDP . Additionally, due to the SNN information being delivered by spikes and generating the output whenever it overcomes the internal threshold value, the SNN exhibits a sparse network state, which has the advantage of low-power consumption in hardware implementation .…”

mentioning

confidence: 99%

Indium–Gallium–Zinc Oxide-Based Synaptic Charge Trap Flash for Spiking Neural Network-Restricted Boltzmann Machine

Park,

Jang,

Noh

et al. 2023

Nano Lett.

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Recently, neuromorphic computing has been proposed to overcome the drawbacks of the current von Neumann computing architecture. Especially, spiking neural network (SNN) has received significant attention due to its ability to mimic the spike-driven behavior of biological neurons and synapses, potentially leading to low-power consumption and other advantages. In this work, we designed the indium–gallium–zinc oxide (IGZO) channel charge-trap flash (CTF) synaptic device based on a HfO2/Al2O3/Si3N4/Al2O3 layer. Our IGZO-based CTF device exhibits synaptic functions with 128 levels of synaptic weight states and spike-timing-dependent plasticity. The SNN–restricted Boltzmann machine was used to simulate the fabricated CTF device to evaluate the efficiency for the SNN system, achieving the high pattern-recognition accuracy of 83.9%. We believe that our results show the suitability of the fabricated IGZO CTF device as a synaptic device for neuromorphic computing.

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Solving Max‐Cut Problem Using Spiking Boltzmann Machine Based on Neuromorphic Hardware with Phase Change Memory

Kang,

Ishii,

Park

et al. 2024

Advanced Science

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Efficiently solving combinatorial optimization problems (COPs) such as Max‐Cut is challenging because the resources required increase exponentially with the problem size. This study proposes a hardware‐friendly method for solving the Max‐Cut problem by implementing a spiking neural network (SNN)‐based Boltzmann machine (BM) in neuromorphic hardware systems. To implement the hardware‐oriented version of the spiking Boltzmann machine (sBM), the stochastic dynamics of leaky integrate‐and‐fire (LIF) neurons with random walk noise are analyzed, and an innovative algorithm based on overlapping time windows is proposed. The simulation results demonstrate the effective convergence and high accuracy of the proposed method for large‐scale Max‐Cut problems. The proposed method is validated through successful hardware implementation on a 6‐transistor/2‐resistor (6T2R) neuromorphic chip with phase change memory (PCM) synapses. In addition, as an expansion of the algorithm, several annealing techniques and bias split methods are proposed to improve convergence, along with circuit design ideas for efficient evaluation of sampling convergence using cell arrays and spiking systems. Overall, the results of the proposed methods demonstrate the potential of energy‐efficient and hardware‐implementable approaches using SNNs to solve COPs. To the best of the author's knowledge, this is the first study to solve the Max‐Cut problem using an SNN neuromorphic hardware chip.

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Pattern Training, Inference, and Regeneration Demonstration Using On‐Chip Trainable Neuromorphic Chips for Spiking Restricted Boltzmann Machine

Cited by 4 publications

References 37 publications

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Indium–Gallium–Zinc Oxide-Based Synaptic Charge Trap Flash for Spiking Neural Network-Restricted Boltzmann Machine

Solving Max‐Cut Problem Using Spiking Boltzmann Machine Based on Neuromorphic Hardware with Phase Change Memory

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