Pattern routing: use and theory for increasing predictability and avoiding coupling

Abstract

Deep submicron effects, along with increasing interconnect densities, have increased the complexity of the routing problem. Whereas previously we could focus on minimizing wirelength, we must now consider a variety of objectives during routing. For example, an increased amount of timing restrictions means that we must minimize interconnect delay. But, interconnect delay is no longer simply related to wirelength. Coupling capacitance has become a dominant component of delay due to the shrinking of device sizes. Regardless, the most important objective is producing a routable circuit. Unfortunately, this often conflicts with minimizing interconnect delay as minimum delay routes create congested areas, for which an exact routing cannot be realized without violating design rules. In this work, we use the concept of pattern routing to develop algorithms that guide the router to a solution that minimizes interconnect delay-by considering both coupling and wirelength-without damaging the routability of the circuit. The paper is divided into two parts. The first part demonstrates that pattern routing can be used without affecting the routability of the circuit. We propose two schemes to choose a set of nets to pattern route. Using these schemes, we show that the routability is not hindered. The second part builds on the previous part by presenting a framework for coupling reduction using pattern routing. We develop theory and algorithms relating pattern routing and coupling. Additionally, we give suggestions on how to extend our theory and use our algorithms for both global and detailed routing.

A Multilevel Congestion-Based Global Router

“…The final solution is obtained by maze routing nets that were unable to be routed using (12). To deal with the few nets that could not be routed by the proposed formulation, the Labyrinth maze router in [36] is used. Information about the RSIR congestion map accuracy is presented in Table 1.…”

Wire density driven global routing for CMP variation and timing

“…• Routability can be estimated by the number of overflow s which indicates that routing demand locally exceeds the available routing capacity [25] [17]. Formal definition of overflow is in [17].…”

“…Formal definition of overflow is in [17]. • Timing is a significant design objective, as interconnect which governs the overall system performance is mainly determined by global routing [13,26].…”

“…The global routing should be an ideal stage for the first order to improve CMP variation as well as timing by optimizing wire density distribution [4,26]. Even though there have been significant amount of work in global routing about crosstalk [4,10,17,18,22,24,30], timing [4,13,26,28] and congestion/routability [1,5,8], none of them has worked on the optimization of wire density distribution for CMP variation and timing.…”

Crosstalk- and performance-driven multilevel full-chip routing

“…Nevertheless, different from the framework of [5] and [24] that integrates global routing, detailed routing, and resource estimation together at each level, our framework performs global routing in the coarsening stage, followed by layer/track assignment in an intermediate stage, and then detailed routing in the uncoarsening stage. At the coarsening stage, a fast congestion-driven pattern routing [20] is used for global routing level by level. After the coarsening stage, we perform layer/track assignment for crosstalk optimization.…”